A 0.23 µg bias instability and 1.6 µg/Hz1/2 resolution silicon oscillating accelerometer with build-in Σ-Δ frequency-to-digital converter

Abstract

This paper presents a silicon oscillating accelerometer (SOA) with CMOS readout circuit. To reduce the bias instability, a PLL is employed to sustain the oscillation instead of the conventional auto-amplitude-control (AAC) circuit. A sigma-delta frequency-to-digital converter (FDC) is built in the PLL to produce the digital output. The MEMS sensor and readout circuit are fabricated in 80 μm SOI and standard 0.35 μm CMOS process, respectively. The SOA achieves 0.23 μg bias instability and 1.6 μg/Hz1/2 resolution with ±30 g full-scale, which are equivalent to 4-ppb relative instability and 27-ppb/Hz1/2resolution. In addition, it only consumes 2.7 mW under a 1.5 V supply.