Pub Date : 2016-09-22DOI: 10.1109/VLSIC.2016.7573501
Yang Xu, P. Kinget
A 0.1-0.6GHz chopping switched-capacitor RF receiver with integrated blocker detector features tunable center frequency, programmable filter order, and very high out-of-band linearity. RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping are achieved by passive SC circuits only. The 34-80mW 65nm receiver achieves 35dB gain, +31dBm OB-IIP3, +15dBm B1dB, and 4.6-9dB NF. The filter order is adapted to blocker power with a blocker detector with a 1us response time.
{"title":"A chopping switched-capacitor RF receiver with integrated blocker detection, +31dBm OB-IIP3, and +15dBm OB-B1dB","authors":"Yang Xu, P. Kinget","doi":"10.1109/VLSIC.2016.7573501","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573501","url":null,"abstract":"A 0.1-0.6GHz chopping switched-capacitor RF receiver with integrated blocker detector features tunable center frequency, programmable filter order, and very high out-of-band linearity. RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping are achieved by passive SC circuits only. The 34-80mW 65nm receiver achieves 35dB gain, +31dBm OB-IIP3, +15dBm B1dB, and 4.6-9dB NF. The filter order is adapted to blocker power with a blocker detector with a 1us response time.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"26 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84394072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-21DOI: 10.1109/VLSIC.2016.7573491
Cheng Huang, T. Kawajiri, H. Ishikuro
In this paper, a 13.56 MHz fully-integrated wireless power transfer system with wireless constant-idle-time control is proposed. The massive off-chip components or wire required for transmitter (TX) voltage regulation in previous works are eliminated. Both wireless and local regulations are achieved with enhanced transient performance and total efficiency, and reduced circuitry and system design complexity. Thanks to the proposed wireless constant-idle-time control technique, an instant load-transient response, and a peak total efficiency of 67.6% with up to 13.7% improvement are observed in measurements with meat between coils at a distance of 6mm.
{"title":"A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants","authors":"Cheng Huang, T. Kawajiri, H. Ishikuro","doi":"10.1109/VLSIC.2016.7573491","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573491","url":null,"abstract":"In this paper, a 13.56 MHz fully-integrated wireless power transfer system with wireless constant-idle-time control is proposed. The massive off-chip components or wire required for transmitter (TX) voltage regulation in previous works are eliminated. Both wireless and local regulations are achieved with enhanced transient performance and total efficiency, and reduced circuitry and system design complexity. Thanks to the proposed wireless constant-idle-time control technique, an instant load-transient response, and a peak total efficiency of 67.6% with up to 13.7% improvement are observed in measurements with meat between coils at a distance of 6mm.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90936150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573555
Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
A 0.58mm2 40nm CMOS message-passing detector (MPD) is designed for a 256-QAM massive MIMO system supporting 32 concurrent mobile users in each time-frequency resource. Leveraging channel hardening in massive MIMO, a symbol hardening technique is proposed to reduce MPD's complexity by more than 60% with minimal SNR loss. The MPD is implemented in a 4-layer 2-way interleaved architecture to enable a 2.76Gb/s throughput (average 4.9 iterations at 27dB SNR with early termination) using 76% smaller area than a fully parallel architecture. With dynamic precision control and clock gating to exploit algorithmic properties, the energy is reduced to 79.8pJ/b (or 2.49pJ/b per TX antenna).
{"title":"A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector","authors":"Wei Tang, Chia-Hsiang Chen, Zhengya Zhang","doi":"10.1109/VLSIC.2016.7573555","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573555","url":null,"abstract":"A 0.58mm2 40nm CMOS message-passing detector (MPD) is designed for a 256-QAM massive MIMO system supporting 32 concurrent mobile users in each time-frequency resource. Leveraging channel hardening in massive MIMO, a symbol hardening technique is proposed to reduce MPD's complexity by more than 60% with minimal SNR loss. The MPD is implemented in a 4-layer 2-way interleaved architecture to enable a 2.76Gb/s throughput (average 4.9 iterations at 27dB SNR with early termination) using 76% smaller area than a fully parallel architecture. With dynamic precision control and clock gating to exploit algorithmic properties, the energy is reduced to 79.8pJ/b (or 2.49pJ/b per TX antenna).","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80073885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573514
A. Agarwal, S. Hsu, M. Anders, S. Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir K. Satpathy, R. Krishnamurthy
A regular expression matching on-die accelerator, consisting of a hybrid deterministic finite automata (HDFA) and Bloom filter (BLM), with measured 2.1GHz operation, is fabricated in 14nm tri-gate CMOS and occupies 0.011mm2. HDFA integrates probability-based truncation, unique transition-state pairs isolation, parallel common transitions detection, and NFA empty transitions. BLM implements a fused 2-hash NOR match bit-line, 1bit read circuits, and sparse H3 hash. These techniques and aging-tolerant read/write register file circuits (120mV/180mV improved VMIN) achieve 350mV-900mV wide dynamic voltage range with peak throughput of 15.2Gbps-17.1Gbps consuming 3.7mW-4.5mW measured at 750mV, 25°C and maximum energy-efficiency of 17.5Tbps/W-12.5Tbps/W measured at near-threshold 350mV.
{"title":"A 350mV–900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS","authors":"A. Agarwal, S. Hsu, M. Anders, S. Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir K. Satpathy, R. Krishnamurthy","doi":"10.1109/VLSIC.2016.7573514","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573514","url":null,"abstract":"A regular expression matching on-die accelerator, consisting of a hybrid deterministic finite automata (HDFA) and Bloom filter (BLM), with measured 2.1GHz operation, is fabricated in 14nm tri-gate CMOS and occupies 0.011mm2. HDFA integrates probability-based truncation, unique transition-state pairs isolation, parallel common transitions detection, and NFA empty transitions. BLM implements a fused 2-hash NOR match bit-line, 1bit read circuits, and sparse H3 hash. These techniques and aging-tolerant read/write register file circuits (120mV/180mV improved VMIN) achieve 350mV-900mV wide dynamic voltage range with peak throughput of 15.2Gbps-17.1Gbps consuming 3.7mW-4.5mW measured at 750mV, 25°C and maximum energy-efficiency of 17.5Tbps/W-12.5Tbps/W measured at near-threshold 350mV.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"95 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79453427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573458
T. Nomoto, Y. Oike, H. Wakabayashi
The evolution of CMOS image sensors (CIS) and the future prospect of a “Sensing” world utilizing advanced imaging technologies promise to improve our quality of life by sensing everything, everywhere, every time. Charge Coupled Device image sensors replaced video camera tubes, allowing the introduction of compact video cameras as consumer products. CIS now dominates the market for digital still cameras created by its predecessor and, with the advent of column-parallel ADCs and back-illuminated technologies, outperforms them. CIS's achieve better signal to noise ratio, lower power consumption, and higher frame rate. Stacked CIS's continue to enhance functionality and user experience in mobile devices, a market that currently comprises over several billion units per year. CIS imaging technologies promise to accelerate the progress of a sensing world by continuously improving sensitivity, extending detectable wave-lengths, and further improving depth resolution and temporal resolution.
{"title":"Accelerating the Sensing world through imaging evolution","authors":"T. Nomoto, Y. Oike, H. Wakabayashi","doi":"10.1109/VLSIC.2016.7573458","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573458","url":null,"abstract":"The evolution of CMOS image sensors (CIS) and the future prospect of a “Sensing” world utilizing advanced imaging technologies promise to improve our quality of life by sensing everything, everywhere, every time. Charge Coupled Device image sensors replaced video camera tubes, allowing the introduction of compact video cameras as consumer products. CIS now dominates the market for digital still cameras created by its predecessor and, with the advent of column-parallel ADCs and back-illuminated technologies, outperforms them. CIS's achieve better signal to noise ratio, lower power consumption, and higher frame rate. Stacked CIS's continue to enhance functionality and user experience in mobile devices, a market that currently comprises over several billion units per year. CIS imaging technologies promise to accelerate the progress of a sensing world by continuously improving sensitivity, extending detectable wave-lengths, and further improving depth resolution and temporal resolution.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"32 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84042208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573485
Somnath Paul, V. Honkote, Ryan Kim, Turbo Majumder, Paolo A. Aseron, V. Grossnickle, R. Sankman, D. Mallik, S. Jain, S. Vangal, J. Tschanz, V. De
A wireless sensor node (WSN) integrates a 0.79mm2 near-threshold voltage (NTV) 32-bit Intel Architecture (IA) microcontroller (MCU) in 14nm tri-gate CMOS, along with solar cell, energy harvester, flash memory, sensors and Bluetooth Low Energy (BLE) radio, to enable always-on always-sensing (AOAS) and advanced edge computing capabilities in Internet-of-Things (IoT) systems. The MCU features four independent voltage-frequency islands (VFI), a low-leakage SRAM array, an on-die oscillator clock source capable of operating at sub-threshold voltage, power gating and multiple active/sleep states, managed by an integrated power management unit (PMU). The MCU operates across a wide frequency (voltage) range of 297MHz (1V) to 0.5MHz (308mV), and achieves a peak energy efficiency of 17pJ/cycle at an optimum supply voltage (VOPT) of 370mV, operating at 3.5MHz. The WSN, powered by a solar cell, demonstrates sustained MHz AOAS operation, consuming only 360μW.
{"title":"An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS","authors":"Somnath Paul, V. Honkote, Ryan Kim, Turbo Majumder, Paolo A. Aseron, V. Grossnickle, R. Sankman, D. Mallik, S. Jain, S. Vangal, J. Tschanz, V. De","doi":"10.1109/VLSIC.2016.7573485","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573485","url":null,"abstract":"A wireless sensor node (WSN) integrates a 0.79mm2 near-threshold voltage (NTV) 32-bit Intel Architecture (IA) microcontroller (MCU) in 14nm tri-gate CMOS, along with solar cell, energy harvester, flash memory, sensors and Bluetooth Low Energy (BLE) radio, to enable always-on always-sensing (AOAS) and advanced edge computing capabilities in Internet-of-Things (IoT) systems. The MCU features four independent voltage-frequency islands (VFI), a low-leakage SRAM array, an on-die oscillator clock source capable of operating at sub-threshold voltage, power gating and multiple active/sleep states, managed by an integrated power management unit (PMU). The MCU operates across a wide frequency (voltage) range of 297MHz (1V) to 0.5MHz (308mV), and achieves a peak energy efficiency of 17pJ/cycle at an optimum supply voltage (VOPT) of 370mV, operating at 3.5MHz. The WSN, powered by a solar cell, demonstrates sustained MHz AOAS operation, consuming only 360μW.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82266167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573559
Xiong Zhou, Qiang Li, S. Kilsgaard, F. Moradi, S. L. Kappel, P. Kidmose
This work reports an ear-EEG acquisition system with dry-contact active electrodes for future wearable applications. Employing dedicated chopper buffer in the active electrodes, a prototype fabricated in a 0.18-μm CMOS demonstrates input impedance as large as 18GΩ@DC and 6.7GΩ@50Hz, and 3.03fA/vHz input current noise, and a total input-referred noise (IRN) of 0.67μVrms in 0.5-100Hz bandwidth. System's CMRR in combination with active electrodes is higher than 100dB@DC. Under large source impedance imbalance of 1MΩ, a 78-dB@50Hz CMRR is still obtained. To validate the system's ability to record EEG, an auditory stead-state response was measured, showing same SNR with wet electrodes and a commercial EEG amplifier.
{"title":"A wearable ear-EEG recording system based on dry-contact active electrodes","authors":"Xiong Zhou, Qiang Li, S. Kilsgaard, F. Moradi, S. L. Kappel, P. Kidmose","doi":"10.1109/VLSIC.2016.7573559","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573559","url":null,"abstract":"This work reports an ear-EEG acquisition system with dry-contact active electrodes for future wearable applications. Employing dedicated chopper buffer in the active electrodes, a prototype fabricated in a 0.18-μm CMOS demonstrates input impedance as large as 18GΩ@DC and 6.7GΩ@50Hz, and 3.03fA/vHz input current noise, and a total input-referred noise (IRN) of 0.67μVrms in 0.5-100Hz bandwidth. System's CMRR in combination with active electrodes is higher than 100dB@DC. Under large source impedance imbalance of 1MΩ, a 78-dB@50Hz CMRR is still obtained. To validate the system's ability to record EEG, an auditory stead-state response was measured, showing same SNR with wet electrodes and a commercial EEG amplifier.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"8 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87009441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573473
Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim
This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2:1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER <; 10<;sup>-12<;/sup> over a -22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm<;sup>2<;/sup>. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm<;sup>2<;/sup>.
{"title":"A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE","authors":"Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim","doi":"10.1109/VLSIC.2016.7573473","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573473","url":null,"abstract":"This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2:1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER <; 10<;sup>-12<;/sup> over a -22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm<;sup>2<;/sup>. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm<;sup>2<;/sup>.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"102 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86444733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573479
Milovan Blagojevic, M. Cochet, Ben Keller, P. Flatresse, A. Vladimirescu, B. Nikolić
This work demonstrates a fully-integrated, compact body-bias generator (BBG) with a fine voltage step and sub-100ns response time for use in process and voltage compensation as well as dynamic energy optimization. The generator is implemented in 28nm UTBB FDSOI, using only 1.0V core and 1.8V IO voltage inputs. A modular design enables easy integration into target mobile SoCs, scalable to power domains of any size. The fine resolution (5mV Vth), 100ns full-scale and 5ns incremental step response, low power (<;10μW), and 1.2% area overhead enable fine-grained adaptive body-biasing (ABB). The ability to dynamically track a target frequency within 1% for 200mV of VCORE change is demonstrated experimentally.
{"title":"A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI","authors":"Milovan Blagojevic, M. Cochet, Ben Keller, P. Flatresse, A. Vladimirescu, B. Nikolić","doi":"10.1109/VLSIC.2016.7573479","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573479","url":null,"abstract":"This work demonstrates a fully-integrated, compact body-bias generator (BBG) with a fine voltage step and sub-100ns response time for use in process and voltage compensation as well as dynamic energy optimization. The generator is implemented in 28nm UTBB FDSOI, using only 1.0V core and 1.8V IO voltage inputs. A modular design enables easy integration into target mobile SoCs, scalable to power domains of any size. The fine resolution (5mV Vth), 100ns full-scale and 5ns incremental step response, low power (<;10μW), and 1.2% area overhead enable fine-grained adaptive body-biasing (ABB). The ability to dynamically track a target frequency within 1% for 200mV of VCORE change is demonstrated experimentally.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"125 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85277716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573482
G. D. Streel, François Stas, Thibaut Gurne, François Durant, C. Frenkel, D. Bol
We propose a UWB transmitter (TX) SoC designed for ultra-low voltage (ULV) in 28nm FDSOI CMOS. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit with embedded power management (PM), highly duty cycled digital baseband, programmable pulse shaping and wide-range on-chip adaptive forward back biasing (FBB) for VT reduction, PVT compensation and tuning of both the carrier frequency (CF) and the output power.
{"title":"SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape","authors":"G. D. Streel, François Stas, Thibaut Gurne, François Durant, C. Frenkel, D. Bol","doi":"10.1109/VLSIC.2016.7573482","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573482","url":null,"abstract":"We propose a UWB transmitter (TX) SoC designed for ultra-low voltage (ULV) in 28nm FDSOI CMOS. Operated at 0.55V, it achieves a record energy efficiency of 14pJ/bit with embedded power management (PM), highly duty cycled digital baseband, programmable pulse shaping and wide-range on-chip adaptive forward back biasing (FBB) for VT reduction, PVT compensation and tuning of both the carrier frequency (CF) and the output power.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"45 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76691854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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