Yan Li, Xiaoling Ding, Haichuan Yang, Xuan Zhang, Yu Gong, Bo Liu
{"title":"A 681 GOPS/W~3.59 TOPS/W CNN Accelerator Based on Novel Data Flow Scheduling Scheme","authors":"Yan Li, Xiaoling Ding, Haichuan Yang, Xuan Zhang, Yu Gong, Bo Liu","doi":"10.1109/ICSICT49897.2020.9278238","DOIUrl":null,"url":null,"abstract":"This paper proposes a deep convolutional neural network(CNN) accelerator for image recognition applications based on a novel data flow scheduling scheme. To accelerate the CNN with high energy efficient, we propose two optimization approaches including: the execution time prediction model based on data balance scheduling, and the dynamic voltage control mechanism. The proposed voltage control mechanism can dynamically configure the working frequency of CNN computing and data accessing respectively. To solve the data imbalance between memory and computing, we optimized the architecture based on approximate computing and data scheduling, and implement a data scheduling scheme by optimizing and adjusting the supply voltage of computing arrays. Implemented under TSMC 45nm process, the proposed accelerator for different CNNs can realize 4/8/16bit data bit width computation. Compared with the state-of-the-art CNN accelerators, it performs 2.70~2.83 times better in energy efficiency.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"95 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper proposes a deep convolutional neural network(CNN) accelerator for image recognition applications based on a novel data flow scheduling scheme. To accelerate the CNN with high energy efficient, we propose two optimization approaches including: the execution time prediction model based on data balance scheduling, and the dynamic voltage control mechanism. The proposed voltage control mechanism can dynamically configure the working frequency of CNN computing and data accessing respectively. To solve the data imbalance between memory and computing, we optimized the architecture based on approximate computing and data scheduling, and implement a data scheduling scheme by optimizing and adjusting the supply voltage of computing arrays. Implemented under TSMC 45nm process, the proposed accelerator for different CNNs can realize 4/8/16bit data bit width computation. Compared with the state-of-the-art CNN accelerators, it performs 2.70~2.83 times better in energy efficiency.