A Novel Page-Forming Scheme with Ultra-Low Bit-Error-Rate and High Reliability on a 1Mb RRAM Chip

Abstract

RRAM is regarded as one of the emerging storage class memory, but the reliability and variability issues still need to be improved. In this work, two-transistors-tow-resistors (2T2R) cell structure and several peripheral circuits are developed, improving the bit-error-rate (BER) significantly. Conventional forming process of RRAM is time consuming, it is another critical issue that should be overcome before mass production. This work proposes a novel flash forming scheme on a specific designed RRAM array. With this verification-free scheme, a page of RRAM cells can be formed simultaneously, reducing the time of forming by orders of magnitude. A 1Mb full chip is designed and fabricated based on the proposed scheme, an ultra-low BER of ~ 10−5 without any error-correction is achieved. Fast speed (<10ns), excellent chip-to-chip uniformity and reliability (>106 cycles, > 10 years@25°C) are also demonstrated on the chip level.