A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation

Abstract

A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for reference-less and lane-independent operation is presented. PI output clock signals that are phase locked to the input data are used for the voltage-controlled oscillator (VCO) frequency locking. The VCO clock signal is then redistributed to the PIs, which triggers bootstrapping between the VCO and PIs. Entire lanes operate independently as in VCO-based parallel reference-less designs, but without performance penalties and with power and area savings. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology, having receiver and transmitter figure-of-merits (mW/Gb/s) of 2.03 and 2.13, respectively.