Pub Date : 2012-12-01DOI: 10.1109/ISOCC.2012.6407063
Yuta Atobe, Youhua Shi, M. Yanagisawa, N. Togawa
Scan test which is one of the useful design for testability techniques is effective for LSIs including cryptographic circuit. It can observe and control the internal states of the circuit under test by using scan chain. However, scan chain presents a significant security risk of information leakage for scan-based attacks which retrieves secret keys of cryptographic LSIs. In this paper, a secure scan architecture against scan-based attack which still has high testability is proposed. In our method, scan data is dynamically changed by adding the latch to any FFs in the scan chain. We show that by using proposed method, neither the secret key nor the testability of an RSA circuit implementation is compromised, and the effectiveness of the proposed method.
{"title":"Dynamically changeable secure scan architecture against scan-based side channel attack","authors":"Yuta Atobe, Youhua Shi, M. Yanagisawa, N. Togawa","doi":"10.1109/ISOCC.2012.6407063","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407063","url":null,"abstract":"Scan test which is one of the useful design for testability techniques is effective for LSIs including cryptographic circuit. It can observe and control the internal states of the circuit under test by using scan chain. However, scan chain presents a significant security risk of information leakage for scan-based attacks which retrieves secret keys of cryptographic LSIs. In this paper, a secure scan architecture against scan-based attack which still has high testability is proposed. In our method, scan data is dynamically changed by adding the latch to any FFs in the scan chain. We show that by using proposed method, neither the secret key nor the testability of an RSA circuit implementation is compromised, and the effectiveness of the proposed method.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129616404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ISOCC.2012.6407088
R. Han, Yaming Zhang, Youngwan Kim, D. Kim, H. Shichijo, K. O. Kenneth
Schottky-barrier diodes fabricated in CMOS without process modification are shown to be suitable for THz imaging. Two THz imagers using a 130-nm digital CMOS technology are demonstrated. A fully-integrated 280-GHz 4×4 imager array exhibits a measured NEP of 29 pW/Hz1/2 and a responsivity of 5.1kV/W (323 V/W without the amplifier). For the first time, electronic-scanning multi-pixel imaging is demonstrated in a setup that does not require bulky and costly optical lenses and mirrors. A second detector operating at 860 GHz is also demonstrated. The detector without an amplifier achieves responsivity of 355 V/W and NEP of 32 pW/Hz1/2. It is shown that the comparable responsivity and NEP as that of 280-GHz detector is due to the improvement of patch antenna efficiency at 860 GHz. The NEP at 860 GHz is 2X better than the best reported performance of MOSFET-based imagers without silicon lens attached to the chip.
{"title":"Terahertz image sensors using CMOS Schottky barrier diodes","authors":"R. Han, Yaming Zhang, Youngwan Kim, D. Kim, H. Shichijo, K. O. Kenneth","doi":"10.1109/ISOCC.2012.6407088","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407088","url":null,"abstract":"Schottky-barrier diodes fabricated in CMOS without process modification are shown to be suitable for THz imaging. Two THz imagers using a 130-nm digital CMOS technology are demonstrated. A fully-integrated 280-GHz 4×4 imager array exhibits a measured NEP of 29 pW/Hz1/2 and a responsivity of 5.1kV/W (323 V/W without the amplifier). For the first time, electronic-scanning multi-pixel imaging is demonstrated in a setup that does not require bulky and costly optical lenses and mirrors. A second detector operating at 860 GHz is also demonstrated. The detector without an amplifier achieves responsivity of 355 V/W and NEP of 32 pW/Hz1/2. It is shown that the comparable responsivity and NEP as that of 280-GHz detector is due to the improvement of patch antenna efficiency at 860 GHz. The NEP at 860 GHz is 2X better than the best reported performance of MOSFET-based imagers without silicon lens attached to the chip.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126451713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6407080
Hoyoung Yoo, Youngjoo Lee, I. Park
The shortened RS code is traditionally decoded based on the standard decoding process by padding zero symbols. As additional cycles are redundantly taken to deal with the zero symbols, the processing latency of the shortened code is almost the same as that of the mother RS code from which the shortened code is derived. A new architecture is proposed in this paper to decrease the processing latency to the codeword length of the shortened RS code, which can be implemented at the cost of small additional hardware resources. The additional hardware complexity is minimized by reutilizing the hardware resources resident in the adjacent block. Experimental results show that the proposed method leads to a significant reduction of the overall latency. For the RS (32, 24) code, the overall processing latency is reduced by 85.2% and 33.6% compared to the conventional and the previous work, respectively. Moreover, the additional hardware complexity of the proposed method is smaller than those of the previous architectures.
{"title":"Low-latency area-efficient decoding architecture for shortened reed-solomon codes","authors":"Hoyoung Yoo, Youngjoo Lee, I. Park","doi":"10.1109/ISOCC.2012.6407080","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407080","url":null,"abstract":"The shortened RS code is traditionally decoded based on the standard decoding process by padding zero symbols. As additional cycles are redundantly taken to deal with the zero symbols, the processing latency of the shortened code is almost the same as that of the mother RS code from which the shortened code is derived. A new architecture is proposed in this paper to decrease the processing latency to the codeword length of the shortened RS code, which can be implemented at the cost of small additional hardware resources. The additional hardware complexity is minimized by reutilizing the hardware resources resident in the adjacent block. Experimental results show that the proposed method leads to a significant reduction of the overall latency. For the RS (32, 24) code, the overall processing latency is reduced by 85.2% and 33.6% compared to the conventional and the previous work, respectively. Moreover, the additional hardware complexity of the proposed method is smaller than those of the previous architectures.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"97 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6406924
O. Klymenko, D. Martynenko, G. Fischer
This paper describes a monolithic integrated single-chip transceiver intended for Impulse Radio (IR) Ultra-wide Band (UWB) applications compliant with the IEEE 802.15.4a standard. The transmitter is designed to operate in the upper UWB band on the mandatory channel #9 (7.9872 GHz). In order to assure compliance with the standard, the transceiver components are designed towards higher degree of integration, low cost and low power consumption operation. The receiver employs a direct down-conversion concept. The transmitter is an implementation of the gated-oscillator-principle to generate short impulses of 2 ns duration. It provides OOK and BPSK modulation capability in accordance with the standard. A fully integrated frequency synthesizer delivers all necessary LO and clock signals for the receiver and the transmitter. In order to minimize the on-chip cross-talk all supply voltages are internally regulated. The circuit was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 2.25 × 2.35 mm2.
{"title":"A highly integrated IR-UWB transceiver for communication and localization","authors":"O. Klymenko, D. Martynenko, G. Fischer","doi":"10.1109/ISOCC.2012.6406924","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6406924","url":null,"abstract":"This paper describes a monolithic integrated single-chip transceiver intended for Impulse Radio (IR) Ultra-wide Band (UWB) applications compliant with the IEEE 802.15.4a standard. The transmitter is designed to operate in the upper UWB band on the mandatory channel #9 (7.9872 GHz). In order to assure compliance with the standard, the transceiver components are designed towards higher degree of integration, low cost and low power consumption operation. The receiver employs a direct down-conversion concept. The transmitter is an implementation of the gated-oscillator-principle to generate short impulses of 2 ns duration. It provides OOK and BPSK modulation capability in accordance with the standard. A fully integrated frequency synthesizer delivers all necessary LO and clock signals for the receiver and the transmitter. In order to minimize the on-chip cross-talk all supply voltages are internally regulated. The circuit was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 2.25 × 2.35 mm2.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127436777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6407092
E. Lim, Zhao Wang, F. Yu, T. Tillo, K. Man, J. Wang, Meng Zhang
Wireless capsule endoscopy (WCE) has conquered some limitations of traditional diagnosing tools, such as the comfortlessness of the cables and the inability of examining small intestine section. However, this technique is still far from satisfactory and requires some feasible improvements. Antenna plays an important role for transmitting and receiving signals. Therefore, the design of a WCE transmitter antenna has been investigated in this paper. Two proposed patch antennas are designed and optimized in this paper. These proposed designs are meeting the requirements for WCE system which includes operating frequency, bandwidth, return loss, and small in size.
{"title":"Transmitter antennas for wireless capsule endoscopy","authors":"E. Lim, Zhao Wang, F. Yu, T. Tillo, K. Man, J. Wang, Meng Zhang","doi":"10.1109/ISOCC.2012.6407092","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407092","url":null,"abstract":"Wireless capsule endoscopy (WCE) has conquered some limitations of traditional diagnosing tools, such as the comfortlessness of the cables and the inability of examining small intestine section. However, this technique is still far from satisfactory and requires some feasible improvements. Antenna plays an important role for transmitting and receiving signals. Therefore, the design of a WCE transmitter antenna has been investigated in this paper. Two proposed patch antennas are designed and optimized in this paper. These proposed designs are meeting the requirements for WCE system which includes operating frequency, bandwidth, return loss, and small in size.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127500689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6407073
Weijie Cheng, J. Cho, Yeonbae Chung
In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-VTH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer standby retention and 4.4× longer write disturbance retention compared to the PMOS-only 2T cell. The memory arrays operate with a logic-compatible supply voltage; /CS controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. Design results from a test chip in a 130 nm logic CMOS technology exhibit the effectiveness of the proposed embedded memory techniques.
{"title":"Design of logic-compatible embedded DRAM using gain memory cell","authors":"Weijie Cheng, J. Cho, Yeonbae Chung","doi":"10.1109/ISOCC.2012.6407073","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407073","url":null,"abstract":"In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-VTH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer standby retention and 4.4× longer write disturbance retention compared to the PMOS-only 2T cell. The memory arrays operate with a logic-compatible supply voltage; /CS controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. Design results from a test chip in a 130 nm logic CMOS technology exhibit the effectiveness of the proposed embedded memory techniques.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123290180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6406900
Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-ook Jung
In this paper, we research on fin thickness (Tfin) and fin height (Hfin) effects on read stability and write ability of tri-gate FinFET based SRAM cell. The degree of drain induced barrier lowering changes with Tfin and fin Hfin. This makes threshold voltage (Vth) vary. Thus, Tfin and Hfin also influence the mean and standard deviation of read static noise margin (RSNM) and word-line write trip voltage (WWTV) since Vth variation is a dominant factor determining them. If Tfin increases, the mean of RSNM (μRSNM) and the mean of WWTV (μWWTV) decreases and increases, respectively, while the standard deviation of RSNM (σRSNM) and WWTV (σWWTV) are almost not changed. If Hfin increases, the μRSNM and μWWTV decreases and increases, respectively, while both σRSNM and σWWTV decrease. However, for a sufficiently small Tfin, the effect of Hfin on μRSNM and μWWTV becomes negligible.
{"title":"Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM","authors":"Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-ook Jung","doi":"10.1109/ISOCC.2012.6406900","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6406900","url":null,"abstract":"In this paper, we research on fin thickness (T<sub>fin</sub>) and fin height (H<sub>fin</sub>) effects on read stability and write ability of tri-gate FinFET based SRAM cell. The degree of drain induced barrier lowering changes with T<sub>fin</sub> and fin H<sub>fin</sub>. This makes threshold voltage (V<sub>th</sub>) vary. Thus, T<sub>fin</sub> and H<sub>fin</sub> also influence the mean and standard deviation of read static noise margin (RSNM) and word-line write trip voltage (WWTV) since V<sub>th</sub> variation is a dominant factor determining them. If T<sub>fin</sub> increases, the mean of RSNM (μ<sub>RSNM</sub>) and the mean of WWTV (μ<sub>WWTV</sub>) decreases and increases, respectively, while the standard deviation of RSNM (σ<sub>RSNM</sub>) and WWTV (σ<sub>WWTV</sub>) are almost not changed. If H<sub>fin</sub> increases, the μ<sub>RSNM</sub> and μ<sub>WWTV</sub> decreases and increases, respectively, while both σ<sub>RSNM</sub> and σ<sub>WWTV</sub> decrease. However, for a sufficiently small T<sub>fin</sub>, the effect of H<sub>fin</sub> on μ<sub>RSNM</sub> and μ<sub>WWTV</sub> becomes negligible.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114455890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6407115
Hoi-Jin Lee, Youngmin Shin, Jae-Cheol Son, T. Han, B. Kong
This paper overviews dual-supply design for low-power mobile systems in deep sub-micron technology. Various dual-supply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dual-supply design applied to a clock network was more efficient than that applied to data-path logics. For example, the dual-supply clock network with clock-gating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clock-gating level converter can enable a system to exploit pulse-based flip-flops without pulse generators, resulting in more power reduction.
{"title":"An efficient dual-supply design for low-power mobile systems","authors":"Hoi-Jin Lee, Youngmin Shin, Jae-Cheol Son, T. Han, B. Kong","doi":"10.1109/ISOCC.2012.6407115","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407115","url":null,"abstract":"This paper overviews dual-supply design for low-power mobile systems in deep sub-micron technology. Various dual-supply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dual-supply design applied to a clock network was more efficient than that applied to data-path logics. For example, the dual-supply clock network with clock-gating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clock-gating level converter can enable a system to exploit pulse-based flip-flops without pulse generators, resulting in more power reduction.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"3 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128537370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a single-chip video display processing SoC design, which is able to provide the complete post-processing solution for Full HD LCD TV. Three novel integrated key techniques have been discussed in detail, including multi-port AXI bus controller, robust film-mode detection and edge-directed content adaptive image interpolation. The overall architecture and algorithms are verified in FPGA platform and fabricated at TSMC 0.13 μm 1P6M CMOS technology node. The SoC chip is also extensively evaluated in a digital HDTV prototype system.
{"title":"Design and implementation of a video display processing SoC for full HD LCD TV","authors":"Hongbin Sun, Longjun Liu, Qiubo Chen, Baolu Zhai, Nanning Zheng","doi":"10.1109/ISOCC.2012.6407099","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407099","url":null,"abstract":"This paper presents a single-chip video display processing SoC design, which is able to provide the complete post-processing solution for Full HD LCD TV. Three novel integrated key techniques have been discussed in detail, including multi-port AXI bus controller, robust film-mode detection and edge-directed content adaptive image interpolation. The overall architecture and algorithms are verified in FPGA platform and fabricated at TSMC 0.13 μm 1P6M CMOS technology node. The SoC chip is also extensively evaluated in a digital HDTV prototype system.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129022427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/ISOCC.2012.6407090
Jae-Young Kim, Ho-Jin Song, K. Ajito, M. Yaita, N. Kukutsu
We present a 300-GHz-band fundamental voltage controlled oscillator (VCO) for wireless communications using 0.25-μm InP HBT technology. The VCO exhibits about -2-dBm differential output power and 10-GHz frequency tuning range with dc power consumption of 46.2 mW. The oscillation frequency band of the VCO can be extended over 360 GHz in the same structure.
{"title":"InP HBT voltage controlled oscillator for 300-GHz-band wireless communications","authors":"Jae-Young Kim, Ho-Jin Song, K. Ajito, M. Yaita, N. Kukutsu","doi":"10.1109/ISOCC.2012.6407090","DOIUrl":"https://doi.org/10.1109/ISOCC.2012.6407090","url":null,"abstract":"We present a 300-GHz-band fundamental voltage controlled oscillator (VCO) for wireless communications using 0.25-μm InP HBT technology. The VCO exhibits about -2-dBm differential output power and 10-GHz frequency tuning range with dc power consumption of 46.2 mW. The oscillation frequency band of the VCO can be extended over 360 GHz in the same structure.","PeriodicalId":300755,"journal":{"name":"2012 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124600411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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