A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) Pub Date : 2000-05-28 DOI:10.1109/ISCAS.2000.856026

A. Doboli, N. Dhanwada, R. Vemuri

引用次数: 6

Abstract

This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.

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从模拟系统的信号流图表示生成系统级架构的启发式技术

本文提出了一种用于模拟系统自动生成不同体系结构的启发式技术。AG迭代生成各种系统网络列表，作为不同的实现，可以实现系统中的信号处理和流。使用简化的估计模块High-Level Performance Estimator (HPE)快速评估所得网络列表的面积和功率。AG算法实现简单。它不像传统的AG技术那样需要广泛的模式库。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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