Design and Implementation of NFC Smart Card SoC with eSTT-MRAM IP

Abstract

In this paper, an eSTT-MRAM-based NFC (Near Field Communication) Smart Card SoC (system-on-chip) architecture compatible with ISO/IEC 14443-A is proposed. ARM SC100 processor is adopted in the SoC, and the system integrates ISO/IEC 14443-A digital baseband controller, clock management module, AES coprocessor and eSTT-MRAM IP, which are connected by the AMBA™ 2.0 bus. The SoC chip is fabricated with SMIC 40nm CMOS technology with an area of 4035.8µm × 2217.4µm. The equivalence gate counts except 4Mb eSTT-MRAM IP are about 600K gates of standard cell, and the average power consumption is 20.1mW@13.56MHz. Measurement results show that the proposed SoC can correctly handle all expected command operations and the technique standards on ISO/IEC 14443-A can be well satisfied.