Alexander Fritsch, Michael Kugel, Rolf Sautter, D. Wendel, J. Pille, O. Torreiter, S. Kalyanasundaram, Daniel Dobson
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引用次数: 6
Abstract
A 4GHz, low latency TCAM in 14nm SOI FinFET technology, using a matchline current sensing scheme with an energy consumption of 0.63 fJ/bit/search at 0.9V and a peak current reduction of 50% compared to voltage sensing implementations. A by entry adjustable search depth allows to reduce power consumption for variable size translation tables. The implemented sandwich floorplan enables an area efficient integration of high performance 0.286μm2 16T-TCAM and 0.143μm2 8T-SRAM cells.
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