A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression

Abstract

This paper proposes a power and area efficient Laplacian Pyramid processing engine (LPPE) for multi-resolution image representation in image/video processing. In the proposed LPPE, a novel FIFO architecture with adaptive data compression is proposed to reduce the power and area consumption of LPPE. A new filtering extension method is also proposed to reduce the output errors. In circuit level, near-threshold design is adopted to further reduce the power consumption by supply voltage scaling. The proposed LPPE fabricated in a 0.18 μm CMOS process technology can process 112 frames per second at 3.68 MHz and 0.5 V while consuming only 452 μW.