{"title":"A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration","authors":"A. Sanyal, Nan Sun","doi":"10.1109/VLSIC.2016.7573465","DOIUrl":null,"url":null,"abstract":"A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"119 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573465","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 25
Abstract
A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.
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