{"title":"A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC","authors":"Sung-En Hsieh, C. Hsieh","doi":"10.1109/VLSIC.2016.7573519","DOIUrl":null,"url":null,"abstract":"A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6-13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"75 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573519","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6-13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.
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