A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback

Abstract

We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.