{"title":"8-bit/color 1024/spl times/768 microdisplay with analog in-pixel pulse width modulation and retinal averaging offset correction","authors":"T. Blalock, N.B. Gaddis, K. Nishimura, T. Knotts","doi":"10.1109/VLSIC.2000.852840","DOIUrl":null,"url":null,"abstract":"A liquid-crystal-on-silicon microdisplay based on a 1024/spl times/768 2-D pixel array fabricated in a digital 0.35 /spl mu/m CMOS process displays images with a color depth of 8-bits/color. The pixel pitch is 22 /spl mu/m and the total chip area is 214 mm/sup 2/. Pixel brightness is controlled by modulating the pulse width of the pixel voltage drive signal with an in-pixel analog pulse width modulation (PWM) circuit which utilizes human optic nerve spatio-temporal averaging to eliminate comparator offset. The 16 million transistor chip displays images at a maximum rate of 85 Hz and has a power dissipation of 200 mW from a single 3.3 V supply.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"4 1","pages":"20-23"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A liquid-crystal-on-silicon microdisplay based on a 1024/spl times/768 2-D pixel array fabricated in a digital 0.35 /spl mu/m CMOS process displays images with a color depth of 8-bits/color. The pixel pitch is 22 /spl mu/m and the total chip area is 214 mm/sup 2/. Pixel brightness is controlled by modulating the pulse width of the pixel voltage drive signal with an in-pixel analog pulse width modulation (PWM) circuit which utilizes human optic nerve spatio-temporal averaging to eliminate comparator offset. The 16 million transistor chip displays images at a maximum rate of 85 Hz and has a power dissipation of 200 mW from a single 3.3 V supply.