{"title":"A Passive Single-Ended-to-Differential-Converter with SAR ADC Achieving 6.1fJ/Conversion-Step","authors":"Mariska van der Struijk, Kevin Pelzers, P. Harpe","doi":"10.1109/MWSCAS47672.2021.9531821","DOIUrl":null,"url":null,"abstract":"This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"288-291"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531821","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.
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