A radiation hardened SRAM cell design in PD-SOI CMOS technology

Yiqi Wang, Ying Li, F. Zhao, Mengxin Liu, Zhengsheng Han
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Abstract

A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.
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基于PD-SOI CMOS技术的抗辐射SRAM电池设计
为了提高SRAM单元的抗单事件干扰能力,在6个晶体管单元的内部锁存节点之间引入了PD-SOI工艺中的miller MOS电容。基于0.35µm PD-SOI CMOS技术中器件物理-基本SPICE模型的6-T SRAM电池的SEU灵敏度SPICE分析表明,该电池的扰动阈值可达到36fC,比未使用米勒电容器的6T提高了33.3%。
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