A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating

Abstract

This work introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 0.9μm2 1T1R bit cell and bit level redundancy is presented. An array efficiency of 50% is achieved with hierarchical bit line design to separate fuse programming from read/sense. A power gating scheme is adopted to reduce leakage current consumption and reduce high voltage exposure for reliability. Program conditions can be optimized for HVM and in-field programming (IFP) to achieve close to 100% bit level yield.