Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis

Ankireddy Nalamalpu, W. Burleson
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引用次数: 54

Abstract

Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take an updated look at repeater insertion in state-of-the-art CMOS, using a new more detailed model. In spite of the more complex model, we present closed form expressions for the delay and the optimal repeater spacing and sizing. Our model is based on the alpha-power law to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Unlike previous work, we model the repeater input as a ramp and accurately model both linear and saturation regions of operation for estimating the propagation delay. Our analytical repeater model is applied for estimating the performance of driving various repeated RC loads and exhibits a maximum error of only 5% when compared with SPICE in a 0.13 /spl mu/m CMOS technology. In practice, it is not always feasible to insert the repeaters at the exact optimal locations along an interconnect. We present a placement sensitivity analysis to quantify the effect of the sub-optimal repeater placement on performance. Closed form expressions are derived to re-size the repeaters to compensate for the sub-optimal placement.
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深亚微米CMOS中继器插入:基于斜坡的分析模型和放置灵敏度分析
在CMOS VLSI中,中继器被广泛用于提高长片上互连的性能。在本文中,我们采用一个新的更详细的模型,对最先进的CMOS中的中继器插入进行了更新的研究。尽管模型比较复杂,但我们给出了延迟和最优中继器间距和尺寸的封闭表达式。我们的模型基于幂律,以考虑深亚微米技术中出现的短通道效应和电阻负载。与以前的工作不同,我们将中继器的输入建模为一个斜坡,并精确地模拟线性和饱和区域的操作,以估计传播延迟。我们的分析中继器模型用于估计驱动各种重复RC负载的性能,与SPICE相比,在0.13 /spl mu/m的CMOS技术中,最大误差仅为5%。在实践中,将中继器插入到沿互连的精确最佳位置并不总是可行的。我们提出了一个放置灵敏度分析来量化次优中继器放置对性能的影响。导出了封闭形式表达式来重新调整中继器的大小,以补偿次优放置。
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