Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection structures

Abstract

Electro-thermal simulation and a laser-interferometric thermal mapping technique are employed to study temperature distribution and dynamics in smart power technology electrostatic discharge (ESD) protection npn transistor devices during a high current stress. The simulation predicts two temperature peaks along the device length which are due to a vertical and lateral current pathway in the studied devices. The temperature distribution in the device is studied via the measurements of the temperature-induced optical phase shift from the device backside. The position of the temperature peaks, their temporal evolution and stress level dependence obtained by experiment and simulation are in good agreement.