Pub Date : 2018-03-01DOI: 10.1109/IRPS.2018.8353536
N. Saxena, S. Mathew, K. Saraswat
Deep neural networks use the computational power of massively parallel processors in applications such as autonomous driving. Autonomous driving demands resiliency (as in safety and reliability) and trillions of operations per second of computing performance to process sensor data with extreme accuracy. This keynote examines various approaches to achieve resiliency in autonomous cars and makes the case for design diversity based redundancy.
{"title":"Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy","authors":"N. Saxena, S. Mathew, K. Saraswat","doi":"10.1109/IRPS.2018.8353536","DOIUrl":"https://doi.org/10.1109/IRPS.2018.8353536","url":null,"abstract":"Deep neural networks use the computational power of massively parallel processors in applications such as autonomous driving. Autonomous driving demands resiliency (as in safety and reliability) and trillions of operations per second of computing performance to process sensor data with extreme accuracy. This keynote examines various approaches to achieve resiliency in autonomous cars and makes the case for design diversity based redundancy.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"8 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90883616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/IRPS.2015.7112657
B. Keeth
This keynote presentation will explore the genesis, architecture and construction of the Hybrid Memory Cube. The presentation will open with a discussion on how both technical and market forces led to the creation of HMC. This will be followed by a dive into the Gen 2 HMC design-detailing the design goals for the device and how manufacturability was a priority from day one. 3D integration is pivotal technology for HMC. As such, it will be explored in the context of key enablers and ongoing challenges. Finally, the presentation will discuss how HMC encompasses a variety of RAS features to improve manufacturability and to ensure long term device reliability.
{"title":"Keynote Address 2: \"Hybrid memory cube: Achieving high performance and high reliability\"","authors":"B. Keeth","doi":"10.1109/IRPS.2015.7112657","DOIUrl":"https://doi.org/10.1109/IRPS.2015.7112657","url":null,"abstract":"This keynote presentation will explore the genesis, architecture and construction of the Hybrid Memory Cube. The presentation will open with a discussion on how both technical and market forces led to the creation of HMC. This will be followed by a dive into the Gen 2 HMC design-detailing the design goals for the device and how manufacturability was a priority from day one. 3D integration is pivotal technology for HMC. As such, it will be explored in the context of key enablers and ongoing challenges. Finally, the presentation will discuss how HMC encompasses a variety of RAS features to improve manufacturability and to ensure long term device reliability.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"25 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87924908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-19DOI: 10.1109/IRPS.2015.7112656
K. Mistry
Traditional transistor scaling drive the semiconductor industry through the 1990s, but led to the era of innovation driven transistor scaling. Strained silicon, high-k plus metal gate transistors, and fin based transistors were some of the key innovations in the last several process technology generations. This presentation will explore both the transistor scaling benefits from these innovations as well as the reliability implications covering the 90nm to 14nm timeframe.
{"title":"Keynote Address 1: \"Transistors and reliability in the innovation era\"","authors":"K. Mistry","doi":"10.1109/IRPS.2015.7112656","DOIUrl":"https://doi.org/10.1109/IRPS.2015.7112656","url":null,"abstract":"Traditional transistor scaling drive the semiconductor industry through the 1990s, but led to the era of innovation driven transistor scaling. Strained silicon, high-k plus metal gate transistors, and fin based transistors were some of the key innovations in the last several process technology generations. This presentation will explore both the transistor scaling benefits from these innovations as well as the reliability implications covering the 90nm to 14nm timeframe.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"315 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2015-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83202443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-15DOI: 10.1109/IRPS.2012.6241834
Guofujun, Zhoujiang, Xieronghua
Telecom system and its reliability are introduced. Approaches in telecom equipment design and manufacture are summarized, such as IC supplier process management, incoming quality control, failure rate and wear-out lifetime evaluation, equipment process online monitor, reliability burn-in and screening, field failure analysis and improvement and so on. Telecom equipment becomes more complicated and integrated and brings engineering challenges to board design with IC component suffering high electrical, temperature and mechanical stress. Flexible and low cost engineering approaches introduced and requirements for IC industry proposed.
{"title":"The reliability approaches and requirements for IC component in telecom system","authors":"Guofujun, Zhoujiang, Xieronghua","doi":"10.1109/IRPS.2012.6241834","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241834","url":null,"abstract":"Telecom system and its reliability are introduced. Approaches in telecom equipment design and manufacture are summarized, such as IC supplier process management, incoming quality control, failure rate and wear-out lifetime evaluation, equipment process online monitor, reliability burn-in and screening, field failure analysis and improvement and so on. Telecom equipment becomes more complicated and integrated and brings engineering challenges to board design with IC component suffering high electrical, temperature and mechanical stress. Flexible and low cost engineering approaches introduced and requirements for IC industry proposed.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"54 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2012-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78000632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-01DOI: 10.1109/IRPS.2012.6241759
J. W. McPherson
{"title":"50 years of IRPS [Banquet Keynote]","authors":"J. W. McPherson","doi":"10.1109/IRPS.2012.6241759","DOIUrl":"https://doi.org/10.1109/IRPS.2012.6241759","url":null,"abstract":"","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2012-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91395403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-10DOI: 10.1109/IRPS.2011.5784438
Ronald G. Filippi, Ping-Chuan Wang, A. Brendler, Paul S. McLaughlin, J. Poulin, B. Redder, James R. Lloyd, James J. Demarest
{"title":"Best Paper Award: The effect of a threshold failure time and bimodal behavior on the electromigration lifetime of copper interconnects","authors":"Ronald G. Filippi, Ping-Chuan Wang, A. Brendler, Paul S. McLaughlin, J. Poulin, B. Redder, James R. Lloyd, James J. Demarest","doi":"10.1109/IRPS.2011.5784438","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784438","url":null,"abstract":"","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89643264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-01DOI: 10.1109/IRPS.2011.5784526
M. Mason, N. Presser, Y. Sin, B. Foran, S. Moss
We investigate the dependence of electron beam induced current (EBIC) contrast from dark-line defects (DLDs) on temperature and voltage bias in failed and degraded high power quantum well laser diodes (HPLDs). Voltage bias induced contrast variations in EBIC allowed us to make the first observation of what may be the DLD initiation point in a degraded, but not failed, HPLD. Wavelet analysis of temperature and voltage dependent EBIC contrast reveals three distinct regions with different defect properties within the DLD. These results can be correlated to destructive physical analysis and other defect characterization techniques, such as cathodoluminescence and deep-level transient spectroscopy, to provide insight into defect types and failure mechanisms in these devices.
{"title":"Electron beam induced current characterization of dark line defects in failed and degraded high power quantum well laser diodes","authors":"M. Mason, N. Presser, Y. Sin, B. Foran, S. Moss","doi":"10.1109/IRPS.2011.5784526","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784526","url":null,"abstract":"We investigate the dependence of electron beam induced current (EBIC) contrast from dark-line defects (DLDs) on temperature and voltage bias in failed and degraded high power quantum well laser diodes (HPLDs). Voltage bias induced contrast variations in EBIC allowed us to make the first observation of what may be the DLD initiation point in a degraded, but not failed, HPLD. Wavelet analysis of temperature and voltage dependent EBIC contrast reveals three distinct regions with different defect properties within the DLD. These results can be correlated to destructive physical analysis and other defect characterization techniques, such as cathodoluminescence and deep-level transient spectroscopy, to provide insight into defect types and failure mechanisms in these devices.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"62 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2010-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80106994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-02DOI: 10.1109/IRPS.2010.5488853
A. Islam, M. Alam
Threshold voltage VT of a transistor degrades with time both due to the formation of defects at the oxide/Si interface, as well as charge trapping into bulk defects - a phenomenon commonly known as Bias Temperature Instability (BTI). However, we have shown earlier that with appropriate mobility vs. vertical effective electric field characteristics, transistor's drivability (i.e., drain current) can be made far less sensitive to the NBTI-induced threshold voltage degradation ΔV T , than previously presumed. Higher steepness of the mobility-field characteristics results in an increase in mobility due to interface defects, which can self-compensate the effect of ΔV T on drain current. In this paper, for the first time we analyze the additional effect of PBTI-induced ΔV T in NMOS transistor parameters and show that mobility at constant gate voltage always increases with PBTI, irrespective of the mobility-field steepness. Therefore, self-compensation for PBTI is even more pronounced compared to NBTI. Next, we demonstrate the consequence of self-compensation via an intuitive analysis in simple digital circuits and show that lifetime of digital ICs increases dramatically once we incorporate the effect of self-compensation by using appropriate sign for mobility variation at constant gate voltage. This might in turn reduce the requirement of different circuit level optimization techniques, currently employed to manage transistor variabilities. Finally, we establish the importance of flatter transfer characteristics for self-compensation, which can be obtained through advanced CMOS technologies.
{"title":"Mobility enhancement due to charge trapping & defect generation: Physics of self-compensated BTI","authors":"A. Islam, M. Alam","doi":"10.1109/IRPS.2010.5488853","DOIUrl":"https://doi.org/10.1109/IRPS.2010.5488853","url":null,"abstract":"Threshold voltage VT of a transistor degrades with time both due to the formation of defects at the oxide/Si interface, as well as charge trapping into bulk defects - a phenomenon commonly known as Bias Temperature Instability (BTI). However, we have shown earlier that with appropriate mobility vs. vertical effective electric field characteristics, transistor's drivability (i.e., drain current) can be made far less sensitive to the NBTI-induced threshold voltage degradation ΔV T , than previously presumed. Higher steepness of the mobility-field characteristics results in an increase in mobility due to interface defects, which can self-compensate the effect of ΔV T on drain current. In this paper, for the first time we analyze the additional effect of PBTI-induced ΔV T in NMOS transistor parameters and show that mobility at constant gate voltage always increases with PBTI, irrespective of the mobility-field steepness. Therefore, self-compensation for PBTI is even more pronounced compared to NBTI. Next, we demonstrate the consequence of self-compensation via an intuitive analysis in simple digital circuits and show that lifetime of digital ICs increases dramatically once we incorporate the effect of self-compensation by using appropriate sign for mobility variation at constant gate voltage. This might in turn reduce the requirement of different circuit level optimization techniques, currently employed to manage transistor variabilities. Finally, we establish the importance of flatter transfer characteristics for self-compensation, which can be obtained through advanced CMOS technologies.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"10 1","pages":"65-72"},"PeriodicalIF":0.0,"publicationDate":"2010-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81648411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173292
M. HigginsRobert
Time-Dependent Dielectric Breakdown (TDDB) data for very thick (8um) silica-based dielectrics is reported at relatively low fields (≪ 5MV/cm) but at extremely high voltages (up to 4000V). TDDB data was taken across a wide range of dielectric thicknesses ranging from 38Å to 8μm (80,000Å). Consistent with the TDDB results generally reported for thin films, a thickness-independent effective dipole moment of ∼13eÅ was concluded from the testing data. TDDB data is also presented for stacked dielectrics structures (Nitride/Silica) which tend to show a strong polarity dependence, depending on whether electron injection is into the nitride or oxide layer. While the time to failure is polarity dependent, the effective dipole moment is independent of polarity.
{"title":"TDDB evaluations and modeling of very high-voltage (10kV) capacitors","authors":"M. HigginsRobert","doi":"10.1109/IRPS.2009.5173292","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173292","url":null,"abstract":"Time-Dependent Dielectric Breakdown (TDDB) data for very thick (8um) silica-based dielectrics is reported at relatively low fields (≪ 5MV/cm) but at extremely high voltages (up to 4000V). TDDB data was taken across a wide range of dielectric thicknesses ranging from 38Å to 8μm (80,000Å). Consistent with the TDDB results generally reported for thin films, a thickness-independent effective dipole moment of ∼13eÅ was concluded from the testing data. TDDB data is also presented for stacked dielectrics structures (Nitride/Silica) which tend to show a strong polarity dependence, depending on whether electron injection is into the nitride or oxide layer. While the time to failure is polarity dependent, the effective dipole moment is independent of polarity.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"45 1","pages":"432-436"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73356436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-10DOI: 10.1109/RELPHY.2000.843910
Vicky O’Donovan, Shay Whiston, A. Deignan, C. N. Chléirigh
The focus of this paper is on the degradation induced by hot-electrons in lateral DMOS transistors. The physical justification for the abandonment of the existing CMOS test methods is explained. Simulation results supporting the hot-carrier phenomenon occurring are reported and both parametrically and experimentally determined hot-electron safe-operation-areas (HE-SOA) are examined for reliable device operation of 20 V LDNMOS and 20 V LDPMOS.
本文重点研究了横向DMOS晶体管中热电子引起的性能退化问题。解释了放弃现有CMOS测试方法的物理理由。本文报道了支持热载流子现象发生的模拟结果，并对20 V LDNMOS和20 V LDPMOS的参数化和实验确定的热电子安全操作区域(HE-SOA)进行了检验。
{"title":"Hot carrier reliability of lateral DMOS transistors","authors":"Vicky O’Donovan, Shay Whiston, A. Deignan, C. N. Chléirigh","doi":"10.1109/RELPHY.2000.843910","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843910","url":null,"abstract":"The focus of this paper is on the degradation induced by hot-electrons in lateral DMOS transistors. The physical justification for the abandonment of the existing CMOS test methods is explained. Simulation results supporting the hot-carrier phenomenon occurring are reported and both parametrically and experimentally determined hot-electron safe-operation-areas (HE-SOA) are examined for reliable device operation of 20 V LDNMOS and 20 V LDPMOS.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":"67 1","pages":"174-179"},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74888895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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