{"title":"Performance of carbon nanotube field effect transistors with doped source and drain extensions and arbitrary geometry","authors":"G. Fiori, G. Iannaccone, Gerhard Klimeck","doi":"10.1109/IEDM.2005.1609397","DOIUrl":null,"url":null,"abstract":"In this work, we investigate the expected device performance and the scaling perspectives of carbon nanotube field effect transistors (CNT-FETs), with doped source and drain extensions, by means of a novel three-dimensional NEGF-based simulation tool capable of considering arbitrary gate geometry and device architecture. In particular, we have investigated short channel effects for different gate configurations and geometry parameters. Double gate devices offer quasi ideal subthreshold slope and DIBL also with not extremely thin gate dielectrics. In addition, we show that devices with parallel CNTs can provide On currents per unit width significantly larger than their silicon counterpart, and that high-frequency performance is very promising","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"13 1","pages":"522-525"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609397","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24
Abstract
In this work, we investigate the expected device performance and the scaling perspectives of carbon nanotube field effect transistors (CNT-FETs), with doped source and drain extensions, by means of a novel three-dimensional NEGF-based simulation tool capable of considering arbitrary gate geometry and device architecture. In particular, we have investigated short channel effects for different gate configurations and geometry parameters. Double gate devices offer quasi ideal subthreshold slope and DIBL also with not extremely thin gate dielectrics. In addition, we show that devices with parallel CNTs can provide On currents per unit width significantly larger than their silicon counterpart, and that high-frequency performance is very promising