Koji Obata, Kazuo Matsukawa, Takuji Miki, Y. Tsukamoto, K. Sushihara
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引用次数: 48
Abstract
A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, Σ modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The ADC consumes 37.1 μW with 100 kHz sampling speed and achieves Schreier's figure of merit (FoMs) of 175.3 dB.
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