A CMOS image sensor for focal-plane low-power motion vector estimation

D. Handoko, Shoji Kawahito, M. Kumahara, Akira Matsuzawa
{"title":"A CMOS image sensor for focal-plane low-power motion vector estimation","authors":"D. Handoko, Shoji Kawahito, M. Kumahara, Akira Matsuzawa","doi":"10.1109/VLSIC.2000.852842","DOIUrl":null,"url":null,"abstract":"This paper presents a CMOS image sensor which captures intermediate pictures at 480 frames/s and a fully accumulated picture at 30 frames/s. The CMOS image sensor is for integrating a low-power motion vector estimation (MVE) engine using the iterative block matching algorithm proposed by the authors.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"13 1","pages":"28-29"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 22

Abstract

This paper presents a CMOS image sensor which captures intermediate pictures at 480 frames/s and a fully accumulated picture at 30 frames/s. The CMOS image sensor is for integrating a low-power motion vector estimation (MVE) engine using the iterative block matching algorithm proposed by the authors.
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一种用于焦平面低功耗运动矢量估计的CMOS图像传感器
本文介绍了一种以480帧/秒的速度捕获中间图像和以30帧/秒的速度捕获全积累图像的CMOS图像传感器。该CMOS图像传感器采用作者提出的迭代块匹配算法集成低功耗运动矢量估计引擎。
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