{"title":"Successive Approximation Register TDC in Time-Mode Signal Processing","authors":"Daniel Junehee Lee, F. Yuan, Yushi Zhou","doi":"10.1109/MWSCAS47672.2021.9531866","DOIUrl":null,"url":null,"abstract":"An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to-time conversion. The architecture, operation, and design details of the TDC are provided. The pseudo-differential signaling of the TDC is examined and timing errors caused by device noise are studied. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the TDC achieves 6.6 ps resolution, 7.1 ENOB, and 0.37 pJ/conversion FOM at 10 MS/s.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"37 1","pages":"945-948"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531866","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to-time conversion. The architecture, operation, and design details of the TDC are provided. The pseudo-differential signaling of the TDC is examined and timing errors caused by device noise are studied. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the TDC achieves 6.6 ps resolution, 7.1 ENOB, and 0.37 pJ/conversion FOM at 10 MS/s.
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