{"title":"A selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories","authors":"H. Kurata, N. Kobayashi, S. Saeki, T. Kawahara","doi":"10.1109/VLSIC.2000.852880","DOIUrl":null,"url":null,"abstract":"The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell's Vth that doesn't degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"117 1","pages":"166-167"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell's Vth that doesn't degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.
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