The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies

Abstract

Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.