Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi
{"title":"A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond","authors":"Y. Tsuji, X. Bai, A. Morioka, M. Miyamura, R. Nebashi, T. Sakamoto, M. Tada, N. Banno, K. Okamoto, N. Iguchi, H. Hada, T. Sugibayashi","doi":"10.1109/VLSIC.2016.7573461","DOIUrl":null,"url":null,"abstract":"Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Programmable Logic (PL) with a high logic density is demonstrated by cross-bar (xbar) of atom switches, which are programmed through logic transistors. The PL has 4 4-input LUTs to minimize area-delay product owing to small area & capacitance of atom switch. Xbar with 50% and 100% populations mixed and programming lines shared architecture achieves a 2× higher logic density comparing to a commercial PL chip on same technology node of 40 nm. 3× higher operation frequency and 40% lower power consumption are also assessed.