Hidetake Sugo, Shunichi Wakashima, R. Kuroda, Y. Yamashita, H. Sumi, Tzu-Jui Wang, Po-Sheng Chou, Ming-Chieh Hsu, S. Sugawa
{"title":"A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wis e connections","authors":"Hidetake Sugo, Shunichi Wakashima, R. Kuroda, Y. Yamashita, H. Sumi, Tzu-Jui Wang, Po-Sheng Chou, Ming-Chieh Hsu, S. Sugawa","doi":"10.1109/VLSIC.2016.7573544","DOIUrl":null,"url":null,"abstract":"An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), ADC and DRAM is developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology for ASIC substrate.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573544","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
An almost 100% temporal aperture (dead-time free) global shutter (GS) stacked CMOS image sensor (CIS) with in-pixel lateral overflow integration capacitor (LOFIC), ADC and DRAM is developed using pixel-wise connections. The prototype chip with 6.6μm-pitch VGA LOFIC pixel dead-time free GS mode and 1.65μm-pitch 4.9M sub-pixel high resolution rolling shutter (RS) mode was fabricated with a 45nm 1P4M CIS technology for PD substrate and a 65nm 1P5M CMOS technology for ASIC substrate.