Residue arithmetic circuits using a signed-digit number representation

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) Pub Date : 2000-05-28 DOI:10.1109/ISCAS.2000.857016

Shugang Wei, K. Shimizu

引用次数: 16

Abstract

A new concept on residue arithmetic using a radix-2 signed-digit (SD) number representation is presented, by which memoryless residue arithmetic circuits using SD adders can be implemented. For a given modulus m, 2/sup p/-1/spl les/m/spl les/2/sup p/+2/sup p-1/-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders. Thus, the module m addition time is independent of the word length of operands. When m=2/sup p/ or m=2/sup p//spl plusmn/1, especially, the module m addition is implemented by only using one SD adder. Moreover, a module m multiplier can be constructed using a binary modulo m SD adder tree, so that the modulo m multiplication can be performed in a time proportional to log/sub 2/p.

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使用符号数字表示的剩余算术电路

提出了一种基于2号符号数表示法的残数运算的新概念，从而实现了基于SD加法器的无记忆残数运算电路。对于给定模m, 2/sup p/-1/spl les/m/spl les/2/sup p/+2/sup p-1/-1，在余数系统(RNS)中，使用两个p位SD加法器进行模m相加。因此，模块m的加法时间与操作数的字长无关。特别是当m=2/sup p/或m=2/sup p//spl plusmn/1时，模块m加法仅使用一个SD加法器实现。此外，可以使用二进制模m SD加法器树构造模m乘法器，使得模m乘法可以在与log/sub 2/p成比例的时间内完成。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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