K. Blutman, A. Kapoor, A. Majumdar, Jacinto Garcia Martinez, J. Echeverri, L. Sevat, A. P. V. D. Wel, H. Fatemi, J. P. D. Gyvez, K. Makinwa
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引用次数: 7
Abstract
This paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR). By using voltage stacking the test chip achieves state-of-the-art (96%) power-conversion efficiency and observed power savings run from 23% to 63% depending upon the payload current, while supply voltage variations are reduced from 5.6mV to 3.8mV (RMS).
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