A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs

Uma Sharma, S. Mahapatra
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引用次数: 1

Abstract

A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔIDLIN) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (VD), gate (VG) and body (VBB) biases is modeled. The framework is also capable of modeling the channel length (LCH) and gate-oxide thickness (TOX) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔIDLIN modeling.
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HCD在HKMG FDSOI mosfet中工艺和偏置依赖性的SPICE兼容紧凑模型
建立了具有高k金属栅极(HKMG)栅极堆叠的28 nm全贫绝缘体上硅(FDSOI) n沟道场效应管在热载流子降解(HCD)应力下线性漏极电流漂移(ΔIDLIN)的时间动力学SPICE兼容模型。对漏极(VD)、栅极(VG)和本体(VBB)偏置的影响进行了建模。该框架还能够对通道长度(LCH)和栅极氧化物厚度(TOX)变化进行建模。在ΔIDLIN建模时也考虑了自热效应(SHE)的影响。
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