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2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)最新文献

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Effect of Stacking Faults on the Thermoelectric Figure of Merit of Si Nanowires 层错对硅纳米线热电性能的影响
K. Vuttivorakulchai, M. Luisier, A. Schenk
The efficiency of converting waste heat to electricity requires a large value of the thermoelectric Figure of merit (ZT). This can be achieved by patterning bulk material into nanostructures like nanowires (NWs). Further improvement results from an increased surface roughness (SR) of such NWs [1]. In this work, Si NWs with stacking faults (SFs) are studied. It is shown that SFs can significantly reduce the lattice thermal conductivity as compared to ideal NWs [2]. A recent derivation of the phonon relaxation time for SF scattering [3] is adapted to the electronic case. It turns out that in most cases the thermoelectric power factor (PF) decreases to a lesser extent than the thermal conductivity. This can double ZT provided that SR scattering of electrons is negligible.
废热转化为电能的效率需要较大的热电性能值(ZT)。这可以通过将块状材料制成纳米结构来实现,比如纳米线(NWs)。进一步的改善来自于这些NWs的表面粗糙度(SR)的增加[1]。本文研究了具有层错(SFs)的NWs。研究表明,与理想的NWs相比,SFs可以显著降低晶格导热系数[2]。最近对SF散射声子弛豫时间的推导[3]适用于电子情况。结果表明,在大多数情况下,热电功率因数(PF)的减小幅度小于导热系数。如果电子的SR散射可以忽略不计,这可以使ZT加倍。
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引用次数: 0
Effect of Trap on Carrier Transport in InAs FET with Al2 O3 Oxide: DFT-based NEGF simulations 陷阱对氧化al_2o_3 InAs FET载流子输运的影响:基于dft的NEGF模拟
M. Shin, Yucheol Cho, S. Jeon
To accurately assess the effect of trap on the performance of field effect transistors (FETs), atom-level first-principles modeling of channel/oxide/trap and rigorous quantum mechanical transport calculations are necessary. In this work we have developed an innovative approach to solve the challenging problem efficiently. Non-equilibrium Green’s function simulation of InAs FET with a trap in the channel/oxide interface that is atomically modeled by using the density functional theory is demonstrated.
为了准确地评估陷阱对场效应晶体管(fet)性能的影响,需要在原子水平上建立沟道/氧化物/陷阱的第一性原理模型和严格的量子力学输运计算。在这项工作中,我们开发了一种创新的方法来有效地解决这个具有挑战性的问题。利用密度泛函理论对具有沟道/氧化物界面陷阱的InAs场效应管进行了非平衡格林函数模拟。
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引用次数: 0
Defect creation and Diffusion under electric fields from first-principles: the prototypical case of silicon dioxide 从第一性原理看电场下缺陷的产生和扩散:二氧化硅的典型案例
N. Salles, L. Martin-Samos, Stefano de Gironcoli, L. Giacomazzi, M. Valant, A. Hémeryck, P. Blaise, B. Sklénard, N. Richard
In this paper we study the effect on the electric fields on the formation of bulk Frenkal Pairs and on the migration of oxygen interstitials, IO, and oxygen vacancies, VO, within the framework of Density Functional Theory and Modern Theory of Polarization. At typical OXRRAM field conditions, We show that a significant effect of the electric field is observed only for charged defect. Analyzing the polarization work, we found anomalously high polarization work, for the case of $mathbf{I}_{mathcal{O}}^{-2}$, with respect to the classical picture of the electric work of an isolated point charge. This large difference has to be ascribed to collective contributions coming from the environment.
本文在密度泛函理论和现代极化理论的框架下,研究了电场对大块Frenkal对的形成以及氧隙IO和氧空位VO迁移的影响。在典型的OXRRAM电场条件下,我们发现电场只对带电缺陷有显著的影响。分析极化功,我们发现$mathbf{I}_{mathcal{O}}^{-2}$的极化功相对于孤立点电荷的电功的经典图像有异常高的极化功。这种巨大的差异必须归因于来自环境的集体贡献。
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引用次数: 0
Electronic and structural properties of interstitial titanium in crystalline silicon from first-principles simulations 晶体硅中间隙钛的电子和结构性质的第一性原理模拟
G. Herrero-Saboya, L. Martin-Samos, A. Hémeryck, D. Rideau, N. Richard
We demonstrate the presence of small Jahn-Teller distortions for interstitial titanium in silicon at different charge states by performing ground state DFT calculations. We prove the existence of three charged transition levels within the band gap by using a non-empirical parameter-free approach, based on the GW approximation, in agreement with DLTS measurements.
我们通过执行基态DFT计算,证明了硅中不同电荷态的间隙钛存在小的Jahn-Teller畸变。我们使用基于GW近似的非经验无参数方法证明了带隙内存在三个带电跃迁能级,与DLTS测量结果一致。
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引用次数: 0
Quantum Transport Simulations of the Zero Temperature Coefficient in Gate-all-around Nanowire pFETs 栅极全能纳米线pfet中零温度系数的量子输运模拟
H. Lee, Junbeom Seo, M. Shin
We present a full quantum transport study of the zero-temperature coefficient (ZTC) point for sub-10 nm gateall-around nanowire p-type field effect transistors (GAA NW pFETs). The phonon scattering effects are included through the self-consistent Born approximation in the non-equilibrium Green’s function framework. The main findings are that the ZTC point can be present in GAA NW pFETs in sub-10 nm regime and the gate voltage at the ZTC point shows an opposite trend and has an upper limit at a certain gate length. This is due to the interplay between the ballisticity ratio and the ballistic current ratio, which can be explained only by the quantum transport simulations.
本文研究了亚10nm栅极全能纳米线p型场效应晶体管(GAA NW pfet)的零温度系数(ZTC)点的全量子输运。在非平衡格林函数框架中,通过自洽玻恩近似包括声子散射效应。研究结果表明:在10 nm以下的区域内,GAA NW pfet中可以出现ZTC点,而ZTC点的栅极电压呈现相反的趋势,并且在一定栅极长度处有上限。这是由于弹道比和弹道电流比之间的相互作用,这只能通过量子输运模拟来解释。
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引用次数: 0
A generalized multi-particle drift-diffusion simulator for optoelectronic devices 用于光电器件的广义多粒子漂移扩散模拟器
D. Rossi, M. Auf der Maur, A. Di Carlo
We present a generalized multi-particle drift-diffusion model capable to overcome the limitations imposed by the classic drift-diffusion model. It was designed as flexible and reusable tool that takes into account explicitly multiple carrier populations, whether charged and neutral, allowing to consider also e.g. exciton transport or ionic motion, crucial for a relevant number of device structures.
本文提出了一种广义多粒子漂移扩散模型,克服了经典漂移扩散模型的局限性。它被设计为灵活和可重复使用的工具,明确考虑到多个载流子种群,无论是带电的还是中性的,也允许考虑例如激子传输或离子运动,对于相关数量的设备结构至关重要。
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引用次数: 0
TCAD Model for Ag-GeSe3-Ni CBRAM Devices Ag-GeSe3-Ni CBRAM器件的TCAD模型
K. Muthuseenu, E. C. Hylin, H. Barnaby, P. Apsangi, M. Kozicki, G. Schlenvogt, Mark A. Townsend
A model for Ag-GeSe3-Ni Conductive Bridge Random Access Memory (CBRAM) device is developed using Technology Computer-Aided Design (TCAD) simulations. A new field-dependent ion mobility saturation model that combines Mott-Gurney ionic transport and a high-field saturation ionic drift velocity model is implemented. Also, an electron mobility model for charge transport through the conductive filament is presented. The model simulates forming and dissolving of the filament at different bias conditions. The simulation results of CBRAM I-V hysteresis curves match well to the experimental data.
采用计算机辅助设计(TCAD)仿真技术建立了Ag-GeSe3-Ni导电桥随机存取存储器(CBRAM)器件的模型。提出了一种结合Mott-Gurney离子输运和高场饱和离子漂移速度模型的场相关离子迁移率饱和模型。此外,还提出了电荷通过导电丝的电子迁移率模型。该模型模拟了不同偏压条件下灯丝的形成和溶解过程。CBRAM I-V滞回曲线的仿真结果与实验数据吻合较好。
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引用次数: 0
A Stochastic Hole Trapping-Detrapping Framework for NBTI, TDDS and RTN NBTI、TDDS和RTN的随机空穴捕获-去捕获框架
S. Bhagdikar, S. Mahapatra
A stochastic framework is presented to model hole trapping and detrapping into and out of individual defects that are present in the gate dielectric of a p-channel MOS transistor. The model calculates thermionic reactions between uncharged and charged states of a defect that are separated by an energy barrier, by using the Gillespie Stochastic Simulation Algorithm (GSSA). The model is validated using experimental data from small area devices under Negative Bias Temperature Instability (NBTI), Random Telegraph Noise (RTN) and Time Dependent Defect Spectroscopy (TDDS) studies.
提出了一个随机框架来模拟p沟道MOS晶体管栅极介电介质中存在的单个缺陷的空穴捕获和脱陷。该模型使用Gillespie随机模拟算法(GSSA)计算了被能量势垒隔开的缺陷的带电和不带电状态之间的热离子反应。在负偏置温度不稳定性(NBTI)、随机电报噪声(RTN)和时间相关缺陷光谱(TDDS)研究下,利用小面积器件的实验数据对该模型进行了验证。
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引用次数: 8
Novel Numerical Dissipation Scheme for Level-Set Based Anisotropic Etching Simulations 基于水平集的各向异性蚀刻模拟的新型数值耗散格式
A. Toifl, Michael Quell, A. Hössinger, A. Babayan, S. Selberherr, J. Weinbub
We propose a novel dissipation scheme for level-set based wet etching simulations. The scheme enables modeling of the temporal evolution of the etch profile during anisotropic wet etching processes and is based on the local geometry and the crystallographic direction-dependent etch rate. We implemented the scheme into Silvaco’s Victory Process simulator which is utilized in this work to simulate the fabrication of source/drain cavities for sub-28 nm strained metal-oxide-semiconductor fieldeffect transistors. Our results show excellent agreement with experimental data. In particular, the main cavity-related design variables are accurately predicted.
我们提出了一种新的基于水平集的湿蚀刻模拟耗散方案。该方案能够模拟各向异性湿法蚀刻过程中蚀刻轮廓的时间演变,并基于局部几何形状和晶体学方向相关的蚀刻速率。我们在Silvaco的Victory Process模拟器中实现了该方案,该模拟器用于模拟亚28nm应变金属氧化物半导体场效应晶体管的源/漏腔的制造。所得结果与实验数据吻合良好。特别是,与空腔相关的主要设计变量得到了准确的预测。
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引用次数: 2
A Robust Simulation Method for Breakdown with Voltage Boundary Condition Utilizing Negative Time Constant Information 基于负时间常数信息的电压边界条件击穿鲁棒仿真方法
S. Kumashiro, Tatsuya Kamei, A. Hiroki, K. Kobayashi
Dominant time constant analysis reveals that the semiconductor equations at hard breakdown turn into a positive feedback state where the convergence of steady state (DC) Newton iteration is substantially difficult even if continuation method is used. A robust simulation method for hard breakdown which detects the appearance of negative time constant during DC Newton iteration and then switches to transient (TR) simulation is proposed. The negative time constant value during the TR simulation is used for the time step restriction and the maximum time constant value is used for the determination of the final time of the TR simulation. By using the proposed method, a trace of the stable operation points in the snapback I-V trajectory corresponding to each DC bias can be obtained robustly with a simple voltage sweep at the voltage boundary.
优势时间常数分析表明,半导体方程在硬击穿时变为正反馈状态,即使采用延拓方法,稳态牛顿迭代的收敛性也相当困难。提出了一种检测直流牛顿迭代过程中出现负时间常数并切换到暂态仿真的硬击穿鲁棒仿真方法。TR模拟时的负时间常数值用于时间步长限制,最大时间常数值用于确定TR模拟的最终时间。利用该方法,通过在电压边界处进行简单的电压扫描,可以鲁棒地获得对应于每个直流偏置的回吸I-V轨迹中稳定工作点的迹线。
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2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
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