Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt
{"title":"Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters","authors":"Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt","doi":"10.1109/ESSCIRC.2015.7313910","DOIUrl":null,"url":null,"abstract":"This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.