Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer
{"title":"80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity","authors":"Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer","doi":"10.1109/VLSIC.2016.7573462","DOIUrl":null,"url":null,"abstract":"An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1998 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
