Hongliang Zhao, Yiqiang Zhao, Yiwei Song, Jun Liao, Junfeng Geng
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引用次数: 5
Abstract
A low power cryogenic readout integrated circuit (ROIC) for mid- and far-wave infrared focal plane array (FPA) is presented as a prototype for 512×512 image system. By applying capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CSD) structure, a high performance readout interface circuit for the infrared FPA is realized with a pixel size of 30×30 µm2. Optimized column readout timing and two operating modes in column amplifiers are used to reduce the power consumption. The readout chip designed by Chartered 0.35 µm 2P4M process shows more than 10 MHz readout rate and less than 70 mW power consumption under 3.3 V supply voltage at 77 K to 150 K operating temperature. And it occupies an area of 18.4×17.5 mm2.
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