Si3N4: HfO2 dual-k spacer dopant-segregated Schottky barrier SOI MOSFET for low-power applications

Abstract

In this paper, it has been shown that employing an underlap channel in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only improves the scalability but also reduces the process induced threshold voltage variability of this device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off a novel Si3N4: HfO2 dual-k spacer underlap channel DSSB SOI MOSFET has also been proposed. Although the presence of HfO2 inner spacer layer increases the gate capacitance, the reduction in off-state leakage current and the improvement in on-state drive current over the conventional Si3N4: SiO2 spacer overlap/underlap channel DSSB SOI MOSFETs makes the proposed device suitable for low-power digital logic circuits.