A fully-adaptive wideband 0.5–32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology

Abstract

This paper describes the design of a low power fully-adaptive wideband, flexible reach transceiver in 16nm FinFET CMOS embedded within FPGA. The receiver utilizes a 3-stage CTLE with a segmented AGC to minimize parasitic peaking and 15-tap DFE to operate over both short and long channels. The transmitter uses a swing boosted CML driver architecture. Low noise wideband fractional N LC PLLs combined with linear active inductor based phase interpolators and high speed clocking are utilized for low jitter clock generation. The transceiver achieves >1200mVdpp TX swing with <;190 fs RJ and 5.39 ps TJ to achieve BER <; 10-15 over a 30 dB loss backplane at 32.75 Gb/s, while consuming 577 mW.