Delay testing and characterization of post-bond interposer wires in 2.5-D ICs

Abstract

Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.