Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651907
Yanjing Li, E. Cheng, S. Makar, S. Mitra
Self-repair replaces/bypasses faulty components in a system-on-chip (SoC) to keep the system functioning correctly even in the presence of permanent faults. Such faults may result from early-life failures, circuit aging, and manufacturing defects and variations. Unlike on-chip memories, processor cores, and networks-on-chip, little attention has been paid to self-repair of uncore components (e.g., cache controllers, memory controllers, and I/O controllers) that occupy significant portions of multi-core SoCs. In this paper, we present new techniques that utilize architectural features to achieve self-repair of uncore components while incurring low area, power, and performance costs. We demonstrate the effectiveness and practicality of our techniques, using the industrial OpenSPARC T2 SoC with 8 processor cores that support 64 hardware threads. Our key results are: 1. Our techniques enable effective self-repair of any single faulty uncore component with 7.5% post-layout chip-level area impact and 3% power impact. In contrast, existing redundancy techniques impose high (e.g., 16%) area costs. Our techniques do not incur any performance impact in fault-free systems. In the presence of a single faulty uncore component, there can be a 5% application performance impact. 2. Our techniques are capable of self-repairing multiple faulty uncore components without any additional area impact, but with graceful degradation of application performance. 3. Our techniques achieve high self-repair coverage of 97.5% in the presence of a single fault. Our self-repair techniques also enable flexible tradeoffs between self-repair coverage and area costs. For example, 75% self-repair coverage can be achieved with 3.2% post-layout chip-level area impact.
{"title":"Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study","authors":"Yanjing Li, E. Cheng, S. Makar, S. Mitra","doi":"10.1109/TEST.2013.6651907","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651907","url":null,"abstract":"Self-repair replaces/bypasses faulty components in a system-on-chip (SoC) to keep the system functioning correctly even in the presence of permanent faults. Such faults may result from early-life failures, circuit aging, and manufacturing defects and variations. Unlike on-chip memories, processor cores, and networks-on-chip, little attention has been paid to self-repair of uncore components (e.g., cache controllers, memory controllers, and I/O controllers) that occupy significant portions of multi-core SoCs. In this paper, we present new techniques that utilize architectural features to achieve self-repair of uncore components while incurring low area, power, and performance costs. We demonstrate the effectiveness and practicality of our techniques, using the industrial OpenSPARC T2 SoC with 8 processor cores that support 64 hardware threads. Our key results are: 1. Our techniques enable effective self-repair of any single faulty uncore component with 7.5% post-layout chip-level area impact and 3% power impact. In contrast, existing redundancy techniques impose high (e.g., 16%) area costs. Our techniques do not incur any performance impact in fault-free systems. In the presence of a single faulty uncore component, there can be a 5% application performance impact. 2. Our techniques are capable of self-repairing multiple faulty uncore components without any additional area impact, but with graceful degradation of application performance. 3. Our techniques achieve high self-repair coverage of 97.5% in the presence of a single fault. Our self-repair techniques also enable flexible tradeoffs between self-repair coverage and area costs. For example, 75% self-repair coverage can be achieved with 3.2% post-layout chip-level area impact.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"25 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75053340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651910
Daniel Chow, Masashi Shimanouchi, Mike P. Li
In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of random jitter (RJ) and random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
{"title":"Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities","authors":"Daniel Chow, Masashi Shimanouchi, Mike P. Li","doi":"10.1109/TEST.2013.6651910","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651910","url":null,"abstract":"In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of random jitter (RJ) and random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"147 6 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83958415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians' knowledge and experience, which, however, have no guarantees nowadays. To tackle this problem, we propose a novel agent-assisted diagnostic framework for board-level functional failures, namely AgentDiag, which facilitates to evaluate the quality of the diagnostic tests and bridge the knowledge gap between the diagnostic programmers who write diagnostic tests and the debug technicians who conduct in-field diagnosis with a lightweight model of the boards and tests. Experimental results on a real industrial board and an OpenRISC design demonstrate the effectiveness of the proposed solution.
{"title":"AgentDiag: An agent-assisted diagnostic framework for board-level functional failures","authors":"Zelong Sun, Li Jiang, Q. Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu","doi":"10.1109/TEST.2013.6651918","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651918","url":null,"abstract":"Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians' knowledge and experience, which, however, have no guarantees nowadays. To tackle this problem, we propose a novel agent-assisted diagnostic framework for board-level functional failures, namely AgentDiag, which facilitates to evaluate the quality of the diagnostic tests and bridge the knowledge gap between the diagnostic programmers who write diagnostic tests and the debug technicians who conduct in-field diagnosis with a lightweight model of the boards and tests. Experimental results on a real industrial board and an OpenRISC design demonstrate the effectiveness of the proposed solution.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"31 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81069436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651878
Takahiro J. Yamaguchi, James S. Tandon, S. Komatsu, K. Asada
A new threshold voltage variation monitoring circuit is introduced which utilizes a stochastic comparator group. It occupies minimal area, only requires a DC input stimulus voltage, and performs digital DC measurement. Traditional methods have required the measurement of the variation in a ring oscillator frequency. Our method circumvents the need for AC measurements, and accelerates the accumulation of data by incorporating stochastic properties into the circuit.
{"title":"A novel test structure for measuring the threshold voltage variance in MOSFETs","authors":"Takahiro J. Yamaguchi, James S. Tandon, S. Komatsu, K. Asada","doi":"10.1109/TEST.2013.6651878","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651878","url":null,"abstract":"A new threshold voltage variation monitoring circuit is introduced which utilizes a stochastic comparator group. It occupies minimal area, only requires a DC input stimulus voltage, and performs digital DC measurement. Traditional methods have required the measurement of the variation in a ring oscillator frequency. Our method circumvents the need for AC measurements, and accelerates the accumulation of data by incorporating stochastic properties into the circuit.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"8 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88855204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651917
J. Ferry
In order to test products, a multi-purpose digital instrument has been developed which can be completely embedded within on-board FPGAs. This instrument incorporates numerous features such as specialized triggering, fault capture, and pattern edge placement. To increase usability, pattern generation and protocol-aware features are included within its small footprint. The applications of the embedded instrument can include design verification, production test, and fault diagnostics in a simple and low resource implementation.
{"title":"FPGA-based universal embedded digital instrument","authors":"J. Ferry","doi":"10.1109/TEST.2013.6651917","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651917","url":null,"abstract":"In order to test products, a multi-purpose digital instrument has been developed which can be completely embedded within on-board FPGAs. This instrument incorporates numerous features such as specialized triggering, fault capture, and pattern edge placement. To increase usability, pattern generation and protocol-aware features are included within its small footprint. The applications of the embedded instrument can include design verification, production test, and fault diagnostics in a simple and low resource implementation.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"5 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73591050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651916
X. Cai, P. Wohl
We present a distributed-multicore hybrid ATPG system which leverages the computing power of multiple machines each with multiple CPUs. The system is versatile and scalable and supports flexible configuration. Experimental results are compared to a highly efficient multicore ATPG system.
{"title":"A distributed-multicore hybrid ATPG system","authors":"X. Cai, P. Wohl","doi":"10.1109/TEST.2013.6651916","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651916","url":null,"abstract":"We present a distributed-multicore hybrid ATPG system which leverages the computing power of multiple machines each with multiple CPUs. The system is versatile and scalable and supports flexible configuration. Experimental results are compared to a highly efficient multicore ATPG system.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"34 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90112124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651919
Z. Conroy, A. Crouch
With shrinking geometries of PCBs, increasing interface speeds and corresponding loss of test point access to diagnose structural test defects, new standard test mechanisms are needed to test chip-to-chip connectivity and functionality at the board level. New requirements for an integrated circuit `BA' (Board-Assist) BIST to structurally test these interfaces will be presented. A standardized BA-BIST template and algorithms for industry leverage are proposed.
{"title":"BA-BIST: Board test from inside the IC out","authors":"Z. Conroy, A. Crouch","doi":"10.1109/TEST.2013.6651919","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651919","url":null,"abstract":"With shrinking geometries of PCBs, increasing interface speeds and corresponding loss of test point access to diagnose structural test defects, new standard test mechanisms are needed to test chip-to-chip connectivity and functionality at the board level. New requirements for an integrated circuit `BA' (Board-Assist) BIST to structurally test these interfaces will be presented. A standardized BA-BIST template and algorithms for industry leverage are proposed.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"126 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85700514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651889
M. Cohn, Kaosio Saechao, Michael Whitlock, Daniel Brenman, Wallace T. Tang, R. Proie
Wide I/O poses serious challenges due to the requisite high density of electronics and relays near the DUT, as well as high bandwidth. A 2×2mm MEMS switch has been demonstrated, offering >80% footprint reduction relative to a typical TO-can electromagnetic relay. A further benefit of its small size, the MEMS relay is able to operate up to Ka-band (40 GHz) with hot switch capability and repeatability of <;±50mΩ. To our knowledge, our latest SPDT device holds the current record in power handling for MEMS devices of 24 W at 10 million cycles.
{"title":"RF MEMS switches for Wide I/O data bus applications","authors":"M. Cohn, Kaosio Saechao, Michael Whitlock, Daniel Brenman, Wallace T. Tang, R. Proie","doi":"10.1109/TEST.2013.6651889","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651889","url":null,"abstract":"Wide I/O poses serious challenges due to the requisite high density of electronics and relays near the DUT, as well as high bandwidth. A 2×2mm MEMS switch has been demonstrated, offering >80% footprint reduction relative to a typical TO-can electromagnetic relay. A further benefit of its small size, the MEMS relay is able to operate up to Ka-band (40 GHz) with hot switch capability and repeatability of <;±50mΩ. To our knowledge, our latest SPDT device holds the current record in power handling for MEMS devices of 24 W at 10 million cycles.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"61 Suppl 1 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77932907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651881
Wei Gao, Chris Liu
SNR enhancement of a 6-band WCDMA/ HSDPA+ directconversion transceiver supporting 21 Mbps High Speed Downlink Packet Access Evolved (HSDPA+) in a single CMOS die is evaluated in this paper. The paper mainly focuses on enhancing SNR performance of a WCDMA/HSDPA+ receiver by minimizing the error vector magnitude (EVM) with the digital compensations of the amplitude and group delay variations of the analog channel selection filter, and bandwidth optimization in the cases of the absence and presence of the adjacent channel interferers (ACIs). The measurement results show that the receiver achieves RX EVM below 3% and 4%, respectively, for WCDMA QPSK and HSDPA+ 64-QAM signals across a very wide input signal power range in all bands, and negligible SNR degradation in the presence of the ACIs.
{"title":"Performance enhancement of a WCDMA/HSDPA+ receiver via minimizing error vector magnitude","authors":"Wei Gao, Chris Liu","doi":"10.1109/TEST.2013.6651881","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651881","url":null,"abstract":"SNR enhancement of a 6-band WCDMA/ HSDPA+ directconversion transceiver supporting 21 Mbps High Speed Downlink Packet Access Evolved (HSDPA+) in a single CMOS die is evaluated in this paper. The paper mainly focuses on enhancing SNR performance of a WCDMA/HSDPA+ receiver by minimizing the error vector magnitude (EVM) with the digital compensations of the amplitude and group delay variations of the analog channel selection filter, and bandwidth optimization in the cases of the absence and presence of the adjacent channel interferers (ACIs). The measurement results show that the receiver achieves RX EVM below 3% and 4%, respectively, for WCDMA QPSK and HSDPA+ 64-QAM signals across a very wide input signal power range in all bands, and negligible SNR degradation in the presence of the ACIs.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"60 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76275657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-04DOI: 10.1109/TEST.2013.6651901
K. Huang, Nathan Kupp, J. Carulli, Y. Makris
Monitoring the semiconductor manufacturing process and understanding the various sources of variation and their repercussions is a crucial capability. Indeed, identifying the root-cause of device failures, enhancing yield of future production through improvement of the manufacturing environment, and providing feedback to the designer toward development of design techniques that minimize failure rate rely on such a capability. To this end, we introduce a spatial decomposition method for breaking down the variation of a wafer to its spatial constituents, based on a small number of measurements sampled across the wafer. We demonstrate that by leveraging domain-specific knowledge and by using as constituents dynamically learned, interpretable basis functions, the ability of the proposed method to accurately identify the sources of variation is drastically improved, as compared to existing approaches. We then illustrate the utility of the proposed spatial variation decomposition method in (i) identifying the main contributor to yield variation, (ii) predicting the actual yield of a wafer, and (iii) clustering wafers for production planning and abnormal wafer identification purposes. Results are reported on industrial data from high-volume manufacturing, confirming the ability of the proposed method to provide great insight regarding the sources of variation in the semiconductor manufacturing process.
{"title":"Process monitoring through wafer-level spatial variation decomposition","authors":"K. Huang, Nathan Kupp, J. Carulli, Y. Makris","doi":"10.1109/TEST.2013.6651901","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651901","url":null,"abstract":"Monitoring the semiconductor manufacturing process and understanding the various sources of variation and their repercussions is a crucial capability. Indeed, identifying the root-cause of device failures, enhancing yield of future production through improvement of the manufacturing environment, and providing feedback to the designer toward development of design techniques that minimize failure rate rely on such a capability. To this end, we introduce a spatial decomposition method for breaking down the variation of a wafer to its spatial constituents, based on a small number of measurements sampled across the wafer. We demonstrate that by leveraging domain-specific knowledge and by using as constituents dynamically learned, interpretable basis functions, the ability of the proposed method to accurately identify the sources of variation is drastically improved, as compared to existing approaches. We then illustrate the utility of the proposed spatial variation decomposition method in (i) identifying the main contributor to yield variation, (ii) predicting the actual yield of a wafer, and (iii) clustering wafers for production planning and abnormal wafer identification purposes. Results are reported on industrial data from high-volume manufacturing, confirming the ability of the proposed method to provide great insight regarding the sources of variation in the semiconductor manufacturing process.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"68 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81109758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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