S. Ryu, C. Capell, Lin Cheng, C. Jonas, A. Gupta, M. Donofrio, J. Clayton, M. O'loughlin, A. Burk, D. Grider, A. Agarwal, J. Palmour, A. Hefner, S. Bhattacharya
{"title":"High performance, ultra high voltage 4H-SiC IGBTs","authors":"S. Ryu, C. Capell, Lin Cheng, C. Jonas, A. Gupta, M. Donofrio, J. Clayton, M. O'loughlin, A. Burk, D. Grider, A. Agarwal, J. Palmour, A. Hefner, S. Bhattacharya","doi":"10.1109/ECCE.2012.6342311","DOIUrl":null,"url":null,"abstract":"We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"19 1","pages":"3603-3608"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"42","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCE.2012.6342311","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 42
Abstract
We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.