Process and layout dependent substrate resistance modeling for deep sub-micron ESD protection devices

Abstract

This paper demonstrates a new methodology for bringing accurate substrate resistance modeling into circuit level ESD simulation. The impact of layout and process variations on the effective substrate resistance of deep sub-micron ESD devices is analyzed and modeled using a quasi mixed-mode approach. The substrate resistance simulated by this method shows good agreement with the values extracted from experimental data. This technique can be employed to simulate turn-on characteristics of ESD protection devices and determine the impact of process and layout variations on their reliability before fabrication of the actual devices.