A 2.57GHz All-Digital Phase-Locked Loop Based on the digital controlled Ring Oscillator

Abstract

This paper presents a 2.57GHz All-Digital Phase-Locked Loop(ADPLL) Based on the digital controlled Ring Oscillator, which uses a frequency and phase detector controller architecture with high resolution and wide locking range. In order to speed up the phase locking, reduce the instantaneous phase locked differential, this dissertation adopts a forward prediction method. The DCO uses 3-stage ring oscillator, the oscillator frequency is controlled by the coarse tune words(CTW) and the fine tune words(FTW), the CTW to control the output frequency fast approaching the target frequency and the FTW to control the final target frequency, in addition, in order to make the DCO work in a linear zone, a normal open oscillation circuit is designed. The layout of the ADPLL circuit is completed by 0.18um CMOS process, which area is 0.3416 mm2 (including pad). The post simulation results show that the maximum output clock frequency is over 2.57GHZ.