{"title":"A high-Psat high-PAE fully-integrated 5.8-GHz power amplifier in 0.18-µm CMOS","authors":"To-Po Wang, Ji-Hong Ke, Cheng-Yu Chiang","doi":"10.1109/EDSSC.2011.6117740","DOIUrl":null,"url":null,"abstract":"A 5.8-GHz 0.18-µm CMOS fully integrated power amplifier (PA) with high saturated output power (Psat), high output 1-dB compressed point (OP1dB), and high power-added efficiency (PAE) is presented in this paper. This PA consists of two stages, the first stage is the single-ended cascode stage for PAE boosting, and the second stage is the cascode power stage for output power enhancement. To further accurately predict the PA performance in terms of power gain, Psat, and PAE, the on-chip passive components including inductors, capacitor, and interconnections are considered by using full-wave electronic-magnetic (EM) tool. From the measured results, the fabricated 5.8-GHz PA delivers 21.4-dBm saturated output power (Psat), 23.6-dB power gain, and 39.7% PAE. Compared to previously published 5.8-GHz 0.18-µm CMOS PAs, this work demonstrated the superior performance in terms of Psat, OP1dB, and PAE.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"4 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117740","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A 5.8-GHz 0.18-µm CMOS fully integrated power amplifier (PA) with high saturated output power (Psat), high output 1-dB compressed point (OP1dB), and high power-added efficiency (PAE) is presented in this paper. This PA consists of two stages, the first stage is the single-ended cascode stage for PAE boosting, and the second stage is the cascode power stage for output power enhancement. To further accurately predict the PA performance in terms of power gain, Psat, and PAE, the on-chip passive components including inductors, capacitor, and interconnections are considered by using full-wave electronic-magnetic (EM) tool. From the measured results, the fabricated 5.8-GHz PA delivers 21.4-dBm saturated output power (Psat), 23.6-dB power gain, and 39.7% PAE. Compared to previously published 5.8-GHz 0.18-µm CMOS PAs, this work demonstrated the superior performance in terms of Psat, OP1dB, and PAE.