A. Brown, Liping Wang, P. Asenov, F. Klüpfel, B. Cheng, S. Martinie, O. Rozeau, S. Barraud, J. Barbe, C. Millar, J. Lorenz
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引用次数: 0
Abstract
A simulation flow for design-technology co-optimisation using 5nm stacked nanowires is presented. The effect of variation in key process parameters on the behaviour of benchmark circuits is examined through the use of variability-aware compact models, accounting for both global and local variability.
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