Hot carrier induced degradation in deep submicron MOSFETs at 100/spl deg/C

Abstract

This work demonstrates that V/sub g/=V/sub d/ is the worst case stress condition for deep submicron NMOSFETs and PMOSFETs operating at 100/spl deg/C. Degradation is more severe at 100/spl deg/C than at room temperature even for supply voltages greater than 2.5 V. The effect of channel length on the substrate current's temperature-dependence is also examined.