A System-On-Chip bus architecture for hardware Trojan protection in security chips

Abstract

Hardware Trojan, similar to the computer viruses, is a new threat in modern System-On-Chips (SOCs) such as security chips and trusted computer systems. Despite the risks that such an attack entails, little attention has been given to the methods of run-time Trojan detection. In this paper, the defects in existing security chips are analyzed and an improved bus architecture for hardware Trojan protection is presented, which can prevent data from runtime Trojan attacking in the digital circuits. A novel bus controller and random number generator (RNG) are used to implement the mechanism and the experimental results shows that the structure is efficient at thwarting the leaking of confidential information and signals.