Y. Frans, Mohamed Elzeftawi, H. Hedayati, J. Im, V. Kireev, Toan Pham, Jaewook Shin, P. Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang
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引用次数: 33
Abstract
A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The receiver consists of continuous-time linear equalizers with constant DC-gain and a 28GSa/s 32-way time-interleaved SAR ADC. The transceiver achieves 1e-8 BER over a backplane channel with 25dB loss at 14GHz while consuming 550mW power, excluding DSP.
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