{"title":"0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications","authors":"B. Tsui, Chia-Pin Lin, Chih-Feng Huang, Y. Xiao","doi":"10.1109/IEDM.2005.1609507","DOIUrl":null,"url":null,"abstract":"Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mum channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"259 1","pages":"911-914"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609507","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 mum channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated
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