Simulation of Statistical NBTI Degradation in 10nm Doped Channel pFinFETs

Abstract

In this paper, by means of simulations, we have studied the impact of Negative Bias Temperature Instability (NBTI) in bulk silicon FinFETs suitable to the 10nm CMOS technology generation. Different levels of channel doping are considered in controlling the threshold voltage and the leakage of the FinFETs for SoC applications. The interplay between the initial statistical variability introduced by random discrete dopants, line edge roughness and metal gate granularity and the statistical variability introduced by different level of trapped charges resulting from NBTI degradation is studied in details. Results related to the time dependent variability and the correlation of key transistor figures of merit are also presented.