1.4 V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) Pub Date : 2000-05-28 DOI:10.1109/ISCAS.2000.857489

J. Ramírez-Angulo, R. Carvajal, J. Martinez-Heredia

引用次数: 24

Abstract

A four quadrant analogue multiplier that operates with a 1.4 V single supply and 0.6 V peak-peak input signals on both inputs is presented. It is based on a new low-voltage class AB differential amplifier with quiescent current control. Current efficiency and random distortion are introduced as quality factors to evaluate the performance of the analog multiplier. The multiplier presented here is characterized by a high current efficiency (50%), high bandwidth (40 MHz) and a high linearity (<1% distortion). Experimental results of a test chip are shown that verify low-voltage, low distortion and wide swing operation. Post layout simulations are presented that verify its wide bandwidth characteristics.

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1.4 V电源，宽摆幅，高电流效率的高频CMOS模拟倍增器

介绍了一种四象限模拟乘法器，该乘法器在1.4 V单电源和0.6 V峰值输入信号下工作。它是基于一种新型的具有静态电流控制的低压AB类差分放大器。引入电流效率和随机失真作为评价模拟乘法器性能的质量因素。本文提出的倍增器具有高电流效率(50%)、高带宽(40 MHz)和高线性度(<1%失真)的特点。实验结果表明，该测试芯片具有低电压、低畸变和宽摆幅的工作特性。通过后布局仿真验证了其宽带特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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